I'm a passionate Design Verification Engineer with hands-on experience in SystemVerilog, UVM, and RTL debugging. I enjoy building scalable, reusable testbenches and solving complex verification challenges across protocols like AXI, FIFO, and memory subsystems.

With a strong foundation in functional coverage, assertions, and CDC verification, I aim to ensure first-silicon success using industry-standard tools such as QuestaSim, VCS, and ModelSim.

• Languages & Methodologies: SystemVerilog, Verilog, UVM, Functional Coverage, Assertions, CDC
• Tools & Platforms: QuestaSim, Synopsys VCS, ModelSim, Gvim, EDA Playground
• Scripting: Shell Scripting, Python (Basic)
• Operating Systems: Linux, Windows

• 📈 Coverage-driven verification and advanced UVM methodologies
• 🧠 Assertion-based verification and RTL debugging
• 🧩 Developing reusable verification components through real-time training at VLSIGuru