diff --git a/docs/images/bad_cable.jpg b/docs/images/bad_cable.jpg new file mode 100644 index 0000000000..60034a388f Binary files /dev/null and b/docs/images/bad_cable.jpg differ diff --git a/docs/images/cable_connectors.jpg b/docs/images/cable_connectors.jpg new file mode 100644 index 0000000000..56ac6ac05c Binary files /dev/null and b/docs/images/cable_connectors.jpg differ diff --git a/docs/images/flash_chip.jpg b/docs/images/flash_chip.jpg new file mode 100644 index 0000000000..38390b8aee Binary files /dev/null and b/docs/images/flash_chip.jpg differ diff --git a/docs/images/flash_headers.jpg b/docs/images/flash_headers.jpg new file mode 100644 index 0000000000..fcb1f4a855 Binary files /dev/null and b/docs/images/flash_headers.jpg differ diff --git a/docs/images/good_cable.jpg b/docs/images/good_cable.jpg new file mode 100644 index 0000000000..8dc7727712 Binary files /dev/null and b/docs/images/good_cable.jpg differ diff --git a/docs/images/pomona_clip_connected_to_flash_chip.jpg b/docs/images/pomona_clip_connected_to_flash_chip.jpg new file mode 100644 index 0000000000..1cbe4935e9 Binary files /dev/null and b/docs/images/pomona_clip_connected_to_flash_chip.jpg differ diff --git a/docs/images/pomona_clip_with_cables.jpg b/docs/images/pomona_clip_with_cables.jpg new file mode 100644 index 0000000000..9e2d30760a Binary files /dev/null and b/docs/images/pomona_clip_with_cables.jpg differ diff --git a/docs/images/pomona_clip_with_rte.jpg b/docs/images/pomona_clip_with_rte.jpg new file mode 100644 index 0000000000..1b39b7931a Binary files /dev/null and b/docs/images/pomona_clip_with_rte.jpg differ diff --git a/docs/images/rte-rpi-testing.jpg b/docs/images/rte-rpi-testing.jpg new file mode 100644 index 0000000000..9b417ea7c5 Binary files /dev/null and b/docs/images/rte-rpi-testing.jpg differ diff --git a/docs/images/rte-rpi.jpg b/docs/images/rte-rpi.jpg new file mode 100644 index 0000000000..aebf20ff0d Binary files /dev/null and b/docs/images/rte-rpi.jpg differ diff --git a/docs/images/vp46xx_location_of_CMOS_header.jpg b/docs/images/vp46xx_location_of_CMOS_header.jpg new file mode 100644 index 0000000000..9f160381e3 Binary files /dev/null and b/docs/images/vp46xx_location_of_CMOS_header.jpg differ diff --git a/docs/images/vp46xx_location_of_flash_chip.jpg b/docs/images/vp46xx_location_of_flash_chip.jpg new file mode 100644 index 0000000000..26bcc28501 Binary files /dev/null and b/docs/images/vp46xx_location_of_flash_chip.jpg differ diff --git a/docs/transparent-validation/msi-z690/laboratory-assembly-guide.md b/docs/transparent-validation/msi-z690/laboratory-assembly-guide.md index 20468e619b..2ffbd47a5e 100644 --- a/docs/transparent-validation/msi-z690/laboratory-assembly-guide.md +++ b/docs/transparent-validation/msi-z690/laboratory-assembly-guide.md @@ -2,8 +2,9 @@ ## Introduction -This document describes the assembly procedure dedicated to the MSI PRO Z690-A -testing stand. +This document describes platform-specific details for assembling an MSI PRO +Z690-A testing stand. Use this document as reference while going through +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) ## Prerequisites @@ -18,27 +19,12 @@ create the testing stand. * USB-UART converter with 4-wire cable * 4-pin header 2.54 mm raster -## Pre-setup activities - -The following subsections describe the method of preparing all the -components of the laboratory stand. - ### MSI PRO Z690-A MSI PRO Z690-A platform should be prepared in accordance with the [Motherboard assembly](presale-assembly-and-validation.md#motherboard-assembly-only) documentation. -### RTE - -RTE (acronym: Remote Testing Environment) should be prepared in accordance with -[Quick start guide](../rte/v1.1.0/quick-start-guide.md) documentation dedicated -to the device. - -### Sonoff - -Prepare Sonoff according to [Sonoff preparation instructions](../sonoff/sonoff_preparation.md) - ## Connections The following sections describe how to enable all of the following features: diff --git a/docs/transparent-validation/msi-z790/laboratory-assembly-guide.md b/docs/transparent-validation/msi-z790/laboratory-assembly-guide.md index 7f584193b8..8f4cbe8529 100644 --- a/docs/transparent-validation/msi-z790/laboratory-assembly-guide.md +++ b/docs/transparent-validation/msi-z790/laboratory-assembly-guide.md @@ -18,27 +18,12 @@ create the testing stand. * USB-UART converter with 4-wire cable * 4-pin header 2.54 mm raster -## Pre-setup activities - -The following subsections describe the method of preparing all the -components of the laboratory stand. - ### MSI PRO Z790-P MSI PRO Z790-P platform should be prepared in accordance with the [Motherboard assembly](../msi-z690/presale-assembly-and-validation.md#motherboard-assembly-only) documentation. -### RTE - -RTE (acronym: Remote Testing Environment) should be prepared in accordance with -[Quick start guide](../rte/v1.1.0/quick-start-guide.md) documentation dedicated -to the device. - -### Sonoff - -Prepare Sonoff according to [Sonoff preparation instructions](../sonoff/sonoff_preparation.md) - ## Connections The following sections describe how to enable all of the following features: diff --git a/docs/transparent-validation/muxpi/basic-validation.md b/docs/transparent-validation/muxpi/basic-validation.md index 0c53e84f75..107810aaf4 100644 --- a/docs/transparent-validation/muxpi/basic-validation.md +++ b/docs/transparent-validation/muxpi/basic-validation.md @@ -250,4 +250,4 @@ Minicom quick guide: --- -_Images source: [Wiki Tizen](https://wiki.tizen.org/MuxPi)_ +_Images source: [Wiki Tizen](http://web.archive.org/web/20230702190152/https://wiki.tizen.org/MuxPi)_ diff --git a/docs/transparent-validation/muxpi/theory-of-operations.md b/docs/transparent-validation/muxpi/theory-of-operations.md index b51e70241d..2cb9357f77 100644 --- a/docs/transparent-validation/muxpi/theory-of-operations.md +++ b/docs/transparent-validation/muxpi/theory-of-operations.md @@ -565,10 +565,10 @@ uart --- Get current value of UART voltage or set if new value is given [in mill --- -_Images source: [Wiki Tizen](https://wiki.tizen.org/MuxPi)_ +_Images source: [Wiki Tizen](http://web.archive.org/web/20230702190152/https://wiki.tizen.org/MuxPi)_ [nanopi-image]: https://cloud.3mdeb.com/index.php/s/MENgScifExeeo6P/download [nanopi-image2]: https://cloud.3mdeb.com/index.php/s/n42rLcAQ5cWcxgW/download [cortex-binary]: https://cloud.3mdeb.com/index.php/s/adnEZLgo2diXkdw/download [etcher]: https://www.balena.io/etcher/ -[usb-m]: https://wiki.tizen.org/MuxPi#USB-M +[usb-m]: http://web.archive.org/web/20230702190152/https://wiki.tizen.org/MuxPi#USB-M diff --git a/docs/transparent-validation/protectli/laboratory-assembly-guide.md b/docs/transparent-validation/protectli/laboratory-assembly-guide.md index 1a24fa9c98..6c7b1229ed 100644 --- a/docs/transparent-validation/protectli/laboratory-assembly-guide.md +++ b/docs/transparent-validation/protectli/laboratory-assembly-guide.md @@ -2,14 +2,15 @@ ## Introduction -This document describes the assembly procedure dedicated to the Protectli -platforms (VP2410, VP2420, VP4630/VP4650/VP4670, V1210/V1410/V1610) testing -stand. +This document describes platform-specific details for assembling Protectli +VP2410, VP2420, VP4630/VP4650/VP4670, V1210/V1410/V1610 testing stands. +Use this document as reference while going through +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) ## Prerequisites -The below table contains information about all elements which are needed to -create the testing stand. +The below table contains platform-specific information about all elements which +are needed to create testing stands for Protectli machines. * [RTE v1.1.0](https://shop.3mdeb.com/shop/open-source-hardware/open-source-hardware-3mdeb/rte/) * RTE power supply 5V 2A Micro-USB @@ -47,131 +48,6 @@ create the testing stand. * Power supply for the platform: 12V 4A * USB-C to USB-A male-male cable for console -## Pre-setup activities - -The following subsections describe the method of preparing all the -components of the laboratory stand. - -### Platform - -The bottom cover has to be removed to connect wires and clips to the platform. - -### RTE - -RTE (acronym: Remote Testing Environment) should be prepared in accordance with -[Quick start guide](../rte/v1.1.0/quick-start-guide.md) documentation dedicated -to the device. - -### Sonoff - -Prepare Sonoff according to [Sonoff preparation -instructions](../sonoff/sonoff_preparation.md) for platforms that require -Sonoff for power control (see [Prerequisites](#prerequisites)). - -## Connections - -The following sections describe how to enable all of the following features: - -* serial connection to the platform, -* controlling power supply, -* enabling basic power actions with the platform (power off/power on/reset), -* external flashing with the RTE, -* CMOS reset circuit. - -### Serial connection - -Depending on platform connect the USB-C or MicroUSB to the platform console -port and the USB-A end to one of the RTE USB-A ports. - -### Power supply controlling - -=== "VP2410" - - Connect 12V power supply to RTE J13 connector, then RTE J12 connector to - DC connector. Do not use any DC jack adapters as these seem to introduce - power losses and noises, making the power connection unstable. - - Picture of the improper cable: - - ![](images/bad_cable.jpg) - - Picture of the proper cable: - - ![](images/good_cable.jpg) - - One has to solder the good cable with the half of bad cable to form a full - cable. Cut the bad cable in half and strip the isolation. Take the red wire - and solder it to the proper cables' white striped wire, this is the hot - wire with positive voltage. Isolate the connection with a tape. Take the - second black wire from the improper cable and solder it to the unstriped - wire of the proper cable. Use tape to isolate and strengthen the whole - connection. The cable is ready. Be sure to use plugs in the following way: - - ![](images/cable_connectors.jpg) - -=== "VP2420" - - Connect 12V power supply to RTE J13 connector, then RTE J12 connector to - DC connector. Do not use any DC jack adapters as these seem to introduce - power losses and noises, making the power connection unstable. - - Picture of the improper cable: - - ![](images/bad_cable.jpg) - - Picture of the proper cable: - - ![](images/good_cable.jpg) - - One has to solder the good cable with the half of bad cable to form a full - cable. Cut the bad cable in half and strip the isolation. Take the red wire - and solder it to the proper cables' white striped wire, this is the hot - wire with positive voltage. Isolate the connection with a tape. Take the - second black wire from the improper cable and solder it to the unstriped - wire of the proper cable. Use tape to isolate and strengthen the whole - connection. The cable is ready. Be sure to use plugs in the following way: - - ![](images/cable_connectors.jpg) - -=== "VP4630/VP4650/VP4670" - - Connect platform power supply EU plug to Sonoff. - -=== "V1210/V1410/V1610" - - Connect 12V power supply to RTE J13 connector, then RTE J12 connector to - DC connector. Do not use any DC jack adapters as these seem to introduce - power losses and noises, making the power connection unstable. - - Picture of the improper cable: - - ![](images/bad_cable.jpg) - - Picture of the proper cable: - - ![](images/good_cable.jpg) - - One has to solder the good cable with the half of bad cable to form a full - cable. Cut the bad cable in half and strip the isolation. Take the red wire - and solder it to the proper cables' white striped wire, this is the hot - wire with positive voltage. Isolate the connection with a tape. Take the - second black wire from the improper cable and solder it to the unstriped - wire of the proper cable. Use tape to isolate and strengthen the whole - connection. The cable is ready. Be sure to use plugs in the following way: - - ![](images/cable_connectors.jpg) - -### Basic power operations enabling - -Connect the RTE J11 header to the platform FP1/F_PANEL1 header using 2.54mm to -2mm wires as described in the table: - -| RTE | Protectli | -|:---------:|:-----------------------------:| -| J11 pin 5 | FP1/F_PANEL1 pin 6 (PWR_ON#) | -| J11 pin 6 | FP1/F_PANEL1 pin 7 (RST#) | -| J15 pin 1 | FP1/F_PANEL1 pin 9 (GND) | - ### External flashing enabling === "VP2410" @@ -254,16 +130,6 @@ Connect the RTE J11 header to the platform FP1/F_PANEL1 header using 2.54mm to Resetting CMOS is required for proper external flashing. -### Complete Setup - -After preparing all of the connections also three activities should be -performed to enable all of the test stand features: - -1. Connect Sonoff to the mains (VP4630/VP4650/VP4670 only). For other - platforms, connect the platform power supply to the mains. -2. Connect the RTE to the Internet by using the Ethernet cable. -3. Connect the RTE to the mains by using the microUSB 5 V/2 A power supply. - ## Theory of operation The following sections describe how to use all of the enabled features: diff --git a/docs/transparent-validation/sd-wire/faq.md b/docs/transparent-validation/sd-wire/faq.md index c9065d0b66..88856d4ac5 100644 --- a/docs/transparent-validation/sd-wire/faq.md +++ b/docs/transparent-validation/sd-wire/faq.md @@ -23,7 +23,7 @@ remote DSLR camera. For additional details please refer to the official documentation: * [Dasharo Universe](https://docs.dasharo.com/transparent-validation/sd-wire/getting-started/) -* [Tizen Wiki](https://wiki.tizen.org/SDWire) +* [Tizen Wiki](http://web.archive.org/web/20240121081917/https://wiki.tizen.org/SDWire) These resources will provide you with comprehensive guidance on how to make the most of the product for your specific needs. diff --git a/docs/transparent-validation/sd-wire/specification.md b/docs/transparent-validation/sd-wire/specification.md index 40d44460a8..47a208374c 100644 --- a/docs/transparent-validation/sd-wire/specification.md +++ b/docs/transparent-validation/sd-wire/specification.md @@ -1,6 +1,8 @@ # Hardware design -Design of this board is based on [SD MUX](https://wiki.tizen.org/SD_MUX). SDWire +Design of this board is based on +[SD MUX](http://web.archive.org/web/20220812002642/https://wiki.tizen.org/SD_MUX) +. SDWire does not have power switch or USB switch but has built in USB SD card reader. SD card multiplexer itself is exactly the same in both devices. @@ -20,7 +22,7 @@ LED positions are showed in the image below. ![](./../../images/SD-wire_leds.jpg) -
Source: [wiki.tizen.org](https://wiki.tizen.org/File:SDWire-leds.png)
+
Source: [wiki.tizen.org](http://web.archive.org/web/20210831025540/https://wiki.tizen.org/File:SDWire-leds.png)
## PCB elements and scheme @@ -30,4 +32,4 @@ LED positions are showed in the image below. ![](./../../images/SD-wire_scheme-1.png) -
Source: [wiki.tizen.org](https://wiki.tizen.org/images/c/cb/SDWire-v1.4-sch.pdf)
+
Source: [wiki.tizen.org](http://web.archive.org/web/20210831025540/https://wiki.tizen.org/images/c/cb/SDWire-v1.4-sch.pdf)
diff --git a/docs/transparent-validation/sd-wire/usage-validation.md b/docs/transparent-validation/sd-wire/usage-validation.md index 27802d255e..05376fd13e 100644 --- a/docs/transparent-validation/sd-wire/usage-validation.md +++ b/docs/transparent-validation/sd-wire/usage-validation.md @@ -276,7 +276,7 @@ Using SDWire there is no need to disconnect SD card from DUT. References & Projects: -* [https://wiki.tizen.org/SDWire](https://wiki.tizen.org/SDWire) +* [Tizen Wiki](http://web.archive.org/web/20240121081917/https://wiki.tizen.org/SDWire) * [Ethernet camera module build – Automated flashing](https://www.kurokesu.com/main/2022/08/02/ethernet-camera-module-build-log-5-automated-flashing/) * [SD Wire & 3d Printer Usage](https://github.com/arekm/OctoPrint-Sdwire) diff --git a/docs/unified-test-documentation/generic-testing-stand-setup.md b/docs/unified-test-documentation/generic-testing-stand-setup.md new file mode 100644 index 0000000000..6d0670599f --- /dev/null +++ b/docs/unified-test-documentation/generic-testing-stand-setup.md @@ -0,0 +1,328 @@ +# Generic testing stand preparation + +## Introduction + +This document aims to provide a comprehensive, generic guide to setting up a +Remote Testing Environment for Dasharo platforms. As you follow along, please +cross-examine with our platform-specific documentation or motherboard +datasheets. + +## Detailed description of the process + +If you are dealing with a new platform, you might want to first dump logs +from it for future reference. We suggest using the dedicated functionality +of +[DTS](https://docs.dasharo.com/common-coreboot-docs/dasharo_tools_suite/). + +### Compiling a list of peripherals + +Before starting to set up the platform in the rack, make sure you plan it +carefully. It is worth first determining what connections should be made on the +stand, and then what equipment we need to be able to do it. When we put the +device in a rack, we want to have remote access to it. Mainly used devices, +depending on the functionalities needed: + +* RTE - if we need low voltage control, switching on or off the platform, + connection via serial and external flashing. +* Sonoff - if we need line voltage control. +* PiKVM - if it is not possible to read the device via serial or it is limited, + it is possible to simulate the keyboard and read the image from HDMI. + +Once we've collected everything, we can move on to setting up the equipment. + +Remember about two important rules while making connections and placing stand +in the rack: + +> **Use ESD Strap**: When assembling and connecting equipment in the lab, it is + essential to use ESD straps. These straps help to prevent electrostatic + discharge and protect sensitive electronic components from damage. Make sure you + wear a strap every time you make a connection, and if someone is helping you, + they have to also wear an ESD strap. +> **Cut off the power supply**: Before making any connections and ensure that the + platform, RTE and any other components are disconnected from power. This + precautionary measure reduces the risk of electrical accidents and protects both + the equipment and you. + +### RTE setup + +You need to examine the platform's motherboard and its manual to determine +whether it has dedicated **SPI headers**, or will you have to use a Pomona clip +to connect to the flash chip. If headers are present, they are preferred over +Pomona connection for stability reasons. + +For exact chip/header locations, see +platform-specific recovery guides in respective +[Supported Hardware](https://docs.dasharo.com/variants/overview/) +subsections. This guide will use Protectli VP46XX as a general example. + +This guide should cover for most of +available platforms, however there are unique exceptions - for example +[MSI boards](https://docs.dasharo.com/unified/msi/recovery/) where we use the +JTPM headers and a FlashBIOS button. Refer to our platform-specific +documentation when in doubt. + +#### Prerequisites + +* [Prepared RTE](../transparent-validation/rte/v1.1.0/quick-start-guide.md) +* SOIC-8 Pomona clip (if applicable) +* 6x female-female wire cables + +#### Connections + +If your motherboard **does not** have SPI headers available, follow this guide +for setting up a Pomona clip connection: + +##### Pomona + +1. Connect the wire cables to the **Pomona clip**. + + ![](../images/pomona_clip.jpg) + ![](../images/pomona_clip_with_cables.jpg) + +1. Connect the Pomona clip to the [SPI header](../transparent-validation/rte/v1.1.0/specification.md) + on RTE. + + | SPI header | Pomona clip | + |:----------:|:------------:| + | Vcc | pin 5 (Vcc) | + | GND | pin 4 (GND) | + | CS | pin 1 (CS) | + | SCLK | pin 7 (CLK) | + | MISO | pin 2 (MISO) | + | MOSI | pin 8 (MOSI) | + + ![](../images/pomona_clip_with_rte.jpg) + +1. Open the platform cover and locate the **SPI flash chip**. + + ![](../images/vp46xx_location_of_flash_chip.jpg) + +1. Match **pin 1(CS)** on the Pomona clip with the first pin of the flash chip, + marked with a small dot engraved on the chip. + + ![](../images/flash_chip.jpg) + ![](../images/pomona_clip_connected_to_flash_chip.jpg) + +##### SPI headers + +If your platform has dedicated SPI flash headers like the Protectli VP66XX, +consider yourself lucky and simply connect corresponding pins with Dupont +wires: + +![](../images/flash_headers.jpg) + +| SPI header | RTE | +|:----------:|:------------:| +| Vcc | Vcc | +| GND | GND | +| CS | CS | +| SCLK | CLK | +| MI**SO** | MI**SO** | +| MO**SI** | MO**SI** | + +##### Remaining pins + +1. Locate **CMOS headers** and wire them to GPIO pins on the RTE. You usually +need to reset the CMOS after flashing for a successful firmware update. +![](../images/vp46xx_location_of_CMOS_header.jpg) + | RTE | DUT | + |:---------:|:--------------------------:| + | J11 pin 8 | CLR_CMOS | + | Any GND | GND | + +1. Locate the power and reset button pins. A motherboard will usually have a +dedicated set of headers where the power and reset button wires are connected. +Connect them to proper pins on the RTE. In extreme cases you might need to use +clips to grab pins of soldered-in power and reset buttons. + + | RTE | DUT | + |:---------:|:-----------------------------:| + | J11 pin 5 | PWR_ON# | + | J11 pin 6 | RST# | + | J15 pin 1 | GND | + +#### DC voltage supply control + +If your device runs on DC voltage up to 24V, power management should be +executed via RTE. Otherwise, skip to [Sonoff setup](#sonoff-setup). + +Connect 12-24V power supply to RTE J13 connector, then RTE J12 connector to +DC connector. Do not use any DC jack adapters as these seem to introduce +power losses and noises, making the power connection unstable. + +Picture of the improper cable: + +![](../images/bad_cable.jpg) + +Picture of the proper cable: + +![](../images/good_cable.jpg) + +You have to solder the good cable with the half of bad cable to form a full +cable. Cut the bad cable in half and strip the isolation. Take the red wire +and solder it to the proper cables' white striped wire, this is the hot +wire with positive voltage. Isolate the connection with a tape. Take the +second black wire from the improper cable and solder it to the unstriped +wire of the proper cable. Use tape to isolate and strengthen the whole +connection. The cable is ready. Be sure to use plugs in the following way: + +![](../images/cable_connectors.jpg) + +### Sonoff setup + +If you require line voltage control, follow our guide for [Sonoff preparation](https://docs.dasharo.com/transparent-validation/sonoff/sonoff_preparation/). + +### PiKVM setup + +If serial connection to the DUT is known to be problematic, follow our guide +for [PiKVM preparation](https://docs.dasharo.com/transparent-validation/pikvm/assembly-and-validation/). + +### Access to the DUT + +Access to the DUT should be realized by connecting the serial port on the DUT +to the serial port on RTE. The location of the serial port should be determined +based on the platform's documentation. Documentation describing this process and +including connections with various cables can be found +[here](https://docs.dasharo.com/transparent-validation/rte/v1.1.0/serial-port-connection-guide/). + +Follow the steps below to configure `ser2net` on RTE, which will allow you to +access the DUT via serial using the telent console. In this example scenario, a +micro USB-USB converter is used to connect the DUT with RTE. + +1. Connect to RTE via ssh. +1. Run the `dmesg -w` command. +1. Disconnect and connect a micro USB-USB converter. +1. On the `dmesg -w` command output look for the attached converter, in this + case: + + ```sh + [ 164.136255] usb 8-1: f81232 converter now attached to ttyUSB0 + ``` + +1. Then use vim to modify settings in `/etc/ser2net.conf` according to the port + received from the `dmesg -w` command, in this case(`ttyUSB0`): + + ```sh + 13541:telnet:1200:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT + ``` + + ```sh + 13542:telnet:1200:/dev/debug_uart_converter:115200 8DATABITS NONE 1STOPBIT + ``` + +1. Check access to the DUT using the `telnet ` command. + +In case it is not possible to read the device via serial, set up PiKVM and +properly connect to the platform. PiKVM setup documentation can be found +[here](https://docs.dasharo.com/transparent-validation/pikvm/assembly-and-validation/). + +#### Platform external flashing + +Platform external flashing is needed for two reasons: + +* it enables quick changes to the firmware, +* it enables the process of unbricking the platform. + +The flashing operation usually consists of several commands, involving crucial +power management, so it is advisable to use our +[osfv-cli tool](https://github.com/Dasharo/osfv-scripts/blob/main/osfv_cli/README.md) +, providing support for most of Dasharo platforms. + +**Example use:** + +```sh +λ osfv_cli rte --rte_ip 192.168.10.244 flash probe +DUT model retrieved from snipeit: VP4630 +Probing flash... +Executing command: flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c MX25L12835F/MX25L12845E/MX25L12865E +flashrom v1.2 on Linux 5.4.69 (armv7l) +flashrom is free software, get the source code at https://flashrom.org + +Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). +Found Macronix flash chip "MX25L12835F/MX25L12845E/MX25L12865E" (16384 kB, SPI) on linux_spi. + +No operations were specified. +``` + +```sh +λ osfv_cli rte --rte_ip 192.168.10.244 flash read --rom vp4630-read.rom +DUT model retrieved from snipeit: VP4630 +Reading from flash... +Executing command: flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c MX25L12835F/MX25L12845E/MX25L12865E -r /tmp/read.rom +flashrom v1.2 on Linux 5.4.69 (armv7l) +flashrom is free software, get the source code at https://flashrom.org + +Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). + +Found Macronix flash chip "MX25L12835F/MX25L12845E/MX25L12865E" (16384 kB, SPI) on linux_spi. + +Reading flash... +done. + +Read flash content saved to vp4630-read.rom +``` + +> Flashing with flashrom takes about 1 minute. + +Note that the first boot of the platform after proceeding with above procedure +can take much longer than usual. + +### Stand Setup + +Before placing the stand in the lab, it is recommended to set it up first at +your desk to verify its functionality. After compiling the stand, the +connections that we have made should be checked. The necessary thing to do the +check is the IP address of RTE which we can get by connecting to RTE via serial +using minicom and using the `ip a` command. + +After this, we have an IP to connect via ssh. This process should suit +every position: + +1. Connect to RTE via ssh. +1. Check access to the DUT using the `telnet ` command from RTE or + log in to PiKVM by entering its IP address in your browser. +1. Check that the commands responsible for the power control are working + properly: + + ```sh + osfv_cli rte --rte_ip 192.168.10.244 rel tgl + ``` + + ```sh + osfv_cli rte --rte_ip 192.168.10.244 pwr on + ``` + + ```sh + osfv_cli rte --rte_ip 192.168.10.244 pwr off + ``` + + ```sh + osfv_cli rte --rte_ip 192.168.10.244 pwr reset + ``` + +1. Check the flashing connections using a prepared flashing script. +1. Check for additional connections. + +### Placement in the Lab + +After testing the functionalities of the stand, follow these guidelines to place +it in the lab: + +1. Select an appropriate location in the rack cabinet for the stand. Consider + safety, accessibility, and proper fastening of the station elements. +1. Ensure that the cables are routed through trays and securely tied to prevent + them from sticking out or becoming tangled. +1. Label the cables and elements of the stand with their IP addresses for easy + identification. +1. Once the stand is in place, recheck the connections, ensuring that all cables + are properly connected and secured. +1. Complete the setup by checking remote access to the stand via SSH and ensure + that all functions are working correctly. + +### Additional steps + +You might want to assign a static IP address for the RTE to avoid connection +problems in the future. It can also prove useful to make a documentation of +your entire test setup and enlist it in an IT asset management system, such as +SnipeIT - providing such information in an issue report might turn out to be +crucial. diff --git a/docs/variants/dell_optiplex/releases.md b/docs/variants/dell_optiplex/releases.md index 86b4edce2a..e8ceaf0aaa 100644 --- a/docs/variants/dell_optiplex/releases.md +++ b/docs/variants/dell_optiplex/releases.md @@ -70,7 +70,7 @@ Software BOM: - [coreboot 4.12-1428-g20cf396c96 (with additional commits for custom platform config and CI YAML)](https://github.com/Dasharo/coreboot/compare/dell_optiplex_9010_v0.0.0...dell_optiplex_9010_v0.0.0) -- [SeaBIOS 1.13.0](https://review.coreboot.org/plugins/gitiles/seabios/+/refs/tags/rel-1.13.0) +- [SeaBIOS 1.13.0](https://web.archive.org/web/20230415000000*/https://review.coreboot.org/plugins/gitiles/seabios/+/refs/tags/rel-1.13.0) #### Binary blobs diff --git a/docs/variants/protectli_vp2410/recovery.md b/docs/variants/protectli_vp2410/recovery.md index e48c0d5aba..ac50f6e81a 100644 --- a/docs/variants/protectli_vp2410/recovery.md +++ b/docs/variants/protectli_vp2410/recovery.md @@ -6,94 +6,35 @@ The following documentation describes the process of recovering hardware from the brick state with [RTE](../../transparent-validation/rte/introduction.md) and Dasharo open-source firmware. -## Prerequisites - -* [Prepared RTE](../../transparent-validation/rte/v1.1.0/quick-start-guide.md) -* SOIC-8 Pomona clip -* 6x female-female wire cables - ## Connections -To prepare the stand for flashing follow the steps described below: - -1. Connect the wire cables to the Pomona clip. - - ![](../../images/protectli_recovery/pomona_clip.jpg) - ![](../../images/protectli_recovery/pomona_clip_with_cables.jpg) - -1. Connect the Pomona clip to the [SPI header](../../transparent-validation/rte/v1.1.0/specification.md) - on RTE. +Set up the connections required for external flashing as described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) +Protectli VP2410 are flashed using the Pomona clip connection variant. Use +the pictures below to easily locate essential components on the mainboard. - | SPI header | Pomona clip | - |:----------:|:------------:| - | Vcc | pin 5 (Vcc) | - | GND | pin 4 (GND) | - | CS | pin 1 (CS) | - | SCLK | pin 7 (CLK) | - | MISO | pin 2 (MISO) | - | MOSI | pin 8 (MOSI) | +### SPI flash chip location - ![](../../images/protectli_recovery/pomona_clip_with_rte.jpg) +Completely remove the motherboard from the platform cover. -1. Completely remove the motherboard from the platform cover. +![](../../images/protectli_recovery/vp2410_disassembly.jpg) +![](../../images/protectli_recovery/vp2410_location_of_flash_chip.jpg) - ![](../../images/protectli_recovery/vp2410_disassembly.jpg) - ![](../../images/protectli_recovery/vp2410_location_of_flash_chip.jpg) +> If there is little thermal paste on the CPU, apply it before reassembling +> the motherboard to the platform cover. - > If there is little thermal paste on the CPU, apply it before reassembling - > the motherboard to the platform cover. +### CMOS header location -1. Match pin 1(CS) on the Pomona clip with the first pin of the one of flash - chip, marked with a small dot engraved on the chip. - - ![](../../images/protectli_recovery/flash_chip.jpg) - ![](../../images/protectli_recovery/pomona_clip_connected_to_flash_chip.jpg) +![](../../images/protectli_recovery/vp2410_location_of_CMOS_header.jpg) ## Firmware flashing -To flash firmware follow the steps described below: - -1. Login to RTE via `ssh` or `minicom`. -1. Turn on the platform by connecting the power supply. -1. Wait at least 5 seconds. -1. Turn off the platform by using the power button. -1. Wait at least 3 seconds. -1. Set the proper state of the SPI by using the following commands on RTE: - - ```bash - # set SPI Vcc to 1.8V - echo 0 > /sys/class/gpio/gpio405/value - # SPI Vcc on - echo 1 > /sys/class/gpio/gpio406/value - # SPI lines ON - echo 1 > /sys/class/gpio/gpio404/value - ``` - -1. Wait at least 2 seconds. -1. Disconnect the power supply from the platform. -1. Wait at least 2 seconds. -1. Flash the platform by using the following command: +To flash firmware, follow the steps described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) +, noting that: +* The chip voltage for this platform is **1.8V** +* The proper flashrom parameters for this platform are: ```bash flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c "MX25U6435E/F" -w [path_to_binary] ``` - - > Flashing with flashrom takes about 1 minute. - -1. Change back the state of the SPI by using the following commands: - - ```bash - echo 0 > /sys/class/gpio/gpio404/value - echo 0 > /sys/class/gpio/gpio406/value - ``` - -1. Reset CMOS, this can be done by two methods: - 1. Disconnect the CMOS battery, wait at least 10 seconds and connect again. - 1. Short the two pins from the CMOS header for at least 10 seconds. - - ![](../../images/protectli_recovery/vp2410_location_of_CMOS_header.jpg) - -1. Turn on the platform by connecting the power supply. - -The first boot of the platform after proceeding with the above procedure can -take much longer than standard. diff --git a/docs/variants/protectli_vp2420/recovery.md b/docs/variants/protectli_vp2420/recovery.md index 630394f7a8..77924dcfe8 100644 --- a/docs/variants/protectli_vp2420/recovery.md +++ b/docs/variants/protectli_vp2420/recovery.md @@ -2,9 +2,10 @@ ## Intro -The following documentation describes the process of recovering hardware from -the brick state with [RTE](../../transparent-validation/rte/introduction.md) and -Dasharo open-source firmware. +The following documentation describes describes platform-specific details of +setting up Protectli VP2420 for recovery from brick state with +[RTE](../../transparent-validation/rte/introduction.md) and Dasharo open-source +firmware. ## Prerequisites @@ -14,82 +15,29 @@ Dasharo open-source firmware. ## Connections -To prepare the stand for flashing follow the steps described below: +Set up the connections required for external flashing as described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md). +Protectli VP2420 are flashed using the Pomona clip connection variant. Use +the pictures below to easily locate essential components on the mainboard. -1. Connect the wire cables to the Pomona clip. +### SPI flash chip - ![](../../images/protectli_recovery/pomona_clip.jpg) - ![](../../images/protectli_recovery/pomona_clip_with_cables.jpg) +![](../../images/protectli_recovery/vp2420_location_of_flash_chip.jpg) +![](../../images/protectli_recovery/flash_chip.jpg) +![](../../images/protectli_recovery/pomona_clip_connected_to_flash_chip.jpg) -1. Connect the Pomona clip to the [SPI header](../../transparent-validation/rte/v1.1.0/specification.md) - on RTE. +### CMOS header - | SPI header | Pomona clip | - |:----------:|:------------:| - | Vcc | pin 5 (Vcc) | - | GND | pin 4 (GND) | - | CS | pin 1 (CS) | - | SCLK | pin 7 (CLK) | - | MISO | pin 2 (MISO) | - | MOSI | pin 8 (MOSI) | - - ![](../../images/protectli_recovery/pomona_clip_with_rte.jpg) - -1. Open the platform cover. - - ![](../../images/protectli_recovery/vp2420_location_of_flash_chip.jpg) - -1. Match pin 1(CS) on the Pomona clip with the first pin of the one of flash - chip, marked with a small dot engraved on the chip. - - ![](../../images/protectli_recovery/flash_chip.jpg) - ![](../../images/protectli_recovery/pomona_clip_connected_to_flash_chip.jpg) +![](../../images/protectli_recovery/vp2420_location_of_CMOS_header.jpg) ## Firmware flashing -To flash firmware follow the steps described below: - -1. Login to RTE via `ssh` or `minicom`. -1. Turn on the platform by connecting the power supply. -1. Wait at least 5 seconds. -1. Turn off the platform by using the power button. -1. Wait at least 3 seconds. -1. Set the proper state of the SPI by using the following commands on RTE: - - ```bash - # set SPI Vcc to 3.3V - echo 1 > /sys/class/gpio/gpio405/value - # SPI Vcc on - echo 1 > /sys/class/gpio/gpio406/value - # SPI lines ON - echo 1 > /sys/class/gpio/gpio404/value - ``` - -1. Wait at least 2 seconds. -1. Disconnect the power supply from the platform. -1. Wait at least 2 seconds. -1. Flash the platform by using the following command: +To flash firmware, follow the steps described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) +, noting that: +* The chip voltage for this platform is **3.3V** +* The proper flashrom parameters for this platform are: ```bash flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c "MX25L12835F/MX25L12845E/MX25L12865E" -w [path_to_binary] ``` - - > Flashing with flashrom takes about 1 minute. - -1. Change back the state of the SPI by using the following commands: - - ```bash - echo 0 > /sys/class/gpio/gpio404/value - echo 0 > /sys/class/gpio/gpio406/value - ``` - -1. Reset CMOS, this can be done by two methods: - 1. Disconnect the CMOS battery, wait at least 10 seconds and connect again. - 1. Short the two pins from the CMOS header for at least 10 seconds. - - ![](../../images/protectli_recovery/vp2420_location_of_CMOS_header.jpg) - -1. Turn on the platform by connecting the power supply. - -The first boot of the platform after proceeding with the above procedure can -take much longer than standard. diff --git a/docs/variants/protectli_vp46xx/recovery.md b/docs/variants/protectli_vp46xx/recovery.md index 527fa12c77..01dfd8fd9f 100644 --- a/docs/variants/protectli_vp46xx/recovery.md +++ b/docs/variants/protectli_vp46xx/recovery.md @@ -2,94 +2,34 @@ ## Intro -The following documentation describes the process of recovering hardware from -the brick state with [RTE](../../transparent-validation/rte/introduction.md) and -Dasharo open-source firmware. - -## Prerequisites - -* [Prepared RTE](../../transparent-validation/rte/v1.1.0/quick-start-guide.md) -* SOIC-8 Pomona clip -* 6x female-female wire cables +The following documentation describes platform-specific details of setting up +Protectli VP46XX for recovery from brick state with +[RTE](../../transparent-validation/rte/introduction.md) +and Dasharo open-source firmware. ## Connections -To prepare the stand for flashing follow the steps described below: - -1. Connect the wire cables to the Pomona clip. - - ![](../../images/protectli_recovery/pomona_clip.jpg) - ![](../../images/protectli_recovery/pomona_clip_with_cables.jpg) - -1. Connect the Pomona clip to the [SPI header](../../transparent-validation/rte/v1.1.0/specification.md) - on RTE. - - | SPI header | Pomona clip | - |:----------:|:------------:| - | Vcc | pin 5 (Vcc) | - | GND | pin 4 (GND) | - | CS | pin 1 (CS) | - | SCLK | pin 7 (CLK) | - | MISO | pin 2 (MISO) | - | MOSI | pin 8 (MOSI) | +Set up the connections required for external flashing as described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md). +Protectli VP46XX are flashed using the Pomona clip connection variant. Use +the pictures below to easily locate essential components on the mainboard. - ![](../../images/protectli_recovery/pomona_clip_with_rte.jpg) +### SPI flash chip location -1. Open the platform cover. +![](../../images/protectli_recovery/vp46xx_location_of_flash_chip.jpg) - ![](../../images/protectli_recovery/vp46xx_location_of_flash_chip.jpg) +### CMOS header location -1. Match pin 1(CS) on the Pomona clip with the first pin of the flash chip, - marked with a small dot engraved on the chip. - - ![](../../images/protectli_recovery/flash_chip.jpg) - ![](../../images/protectli_recovery/pomona_clip_connected_to_flash_chip.jpg) +![](../../images/protectli_recovery/vp46xx_location_of_CMOS_header.jpg) ## Firmware flashing -To flash firmware follow the steps described below: - -1. Login to RTE via `ssh` or `minicom`. -1. Turn on the platform by connecting the power supply. -1. Wait at least 5 seconds. -1. Turn off the platform by using the power button. -1. Wait at least 3 seconds. -1. Set the proper state of the SPI by using the following commands on RTE: - - ```bash - # set SPI Vcc to 3.3V - echo 1 > /sys/class/gpio/gpio405/value - # SPI Vcc on - echo 1 > /sys/class/gpio/gpio406/value - # SPI lines ON - echo 1 > /sys/class/gpio/gpio404/value - ``` - -1. Wait at least 2 seconds. -1. Disconnect the power supply from the platform. -1. Wait at least 2 seconds. -1. Flash the platform by using the following command: +To flash firmware, follow the steps described in +[Generic Testing Stand Setup](../../unified-test-documentation/generic-testing-stand-setup.md) +, noting that: +* The chip voltage for this platform is **3.3V** +* The proper flashrom parameters for this platform are: ```bash flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c "MX25L12835F/MX25L12845E/MX25L12865E" -w [path_to_binary] ``` - - > Flashing with flashrom takes about 1 minute. - -1. Change back the state of the SPI by using the following commands: - - ```bash - echo 0 > /sys/class/gpio/gpio404/value - echo 0 > /sys/class/gpio/gpio406/value - ``` - -1. Reset CMOS, this can be done by two methods: - 1. Disconnect the CMOS battery, wait at least 10 seconds and connect again. - 1. Short the two pins from the CMOS header for at least 10 seconds. - - ![](../../images/protectli_recovery/vp46xx_location_of_CMOS_header.jpg) - -1. Turn on the platform by connecting the power supply. - -The first boot of the platform after proceeding with the above procedure can -take much longer than standard. diff --git a/docs/variants/supermicro_x11_lga1151_series/releases.md b/docs/variants/supermicro_x11_lga1151_series/releases.md index 2a61fefe72..29cab55768 100644 --- a/docs/variants/supermicro_x11_lga1151_series/releases.md +++ b/docs/variants/supermicro_x11_lga1151_series/releases.md @@ -70,7 +70,7 @@ Software BOM: - [coreboot 4.12-1428-g20cf396c96 (with additional commits for custom platform config and CI YAML)](https://github.com/Dasharo/coreboot/compare/dell_optiplex_9010_v0.0.0...dell_optiplex_9010_v0.0.0) -- [SeaBIOS 1.13.0](https://review.coreboot.org/plugins/gitiles/seabios/+/refs/tags/rel-1.13.0) +- [SeaBIOS 1.13.0](https://web.archive.org/web/20230415000000*/https://review.coreboot.org/plugins/gitiles/seabios/+/refs/tags/rel-1.13.0) #### Binary blobs diff --git a/mkdocs.yml b/mkdocs.yml index 484a3c38da..ab6ad2f24b 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -410,6 +410,7 @@ nav: - 'Dasharo Test Specification': - 'Overview': unified-test-documentation/overview.md - 'Generic Test Setup': unified-test-documentation/generic-test-setup.md + - 'Generic Testing Stand Setup': unified-test-documentation/generic-testing-stand-setup.md - 'Dasharo compatibility': - 'Coreboot Base Port': unified-test-documentation/dasharo-compatibility/100-coreboot-base-port.md - 'Memory HCL': unified-test-documentation/dasharo-compatibility/301-memory-hcl.md