diff --git a/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md b/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md
index 65ea55b..c1b3804 100644
--- a/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md
+++ b/Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md
@@ -1,90 +1,107 @@
-THIS OUTLINE IS INCOMPLETE
-
-# IF Connection Module #
+# IF Connection Module
 (Verilog module known as Con_IF)
 
 ## Contents
+* [Overview](#overview)
 * [Inputs](#inputs)
 * [Outputs](#outputs)
 * [Modules](#modules)
   * [PC](#pc)
   * [Instruction Cache](#instruction_cache)
 * [Internal Connections](#internal_connections)
+* [Workflows](#workflows)
+  * [PC Update Process](#pc-update-process)
+  * [Instruction Fetch Process](#instruction-fetch-process)
+  * [Memory Access Process](#memory-access-process)
+
+## Overview
+The IF Connection Module (`Con_IF`) is responsible for managing the instruction fetch stage of the pipeline. It includes the `PC` module for tracking the program counter and the `Instruction Cache` module for storing and retrieving instructions efficiently.
 
 ## Inputs
-|Name|Bits wide|
-|:---|:---:|
-|```clk```|1-bit|
-|```cache_clk```|1-bit|
-|```rstn```|1-bit|
-|```rstn_h```|1-bit|
-|```pc_en```|1-bit|
-|```npc```|32-bit|
+| Name | Bits wide | Description |
+|:---|:---:|:---|
+| `clk` | 1-bit | Global clock signal |
+| `cache_clk` | 1-bit | Dedicated clock for the instruction cache |
+| `rstn` | 1-bit | Active-low reset for the PC module |
+| `rstn_h` | 1-bit | Active-low reset for the Instruction Cache |
+| `pc_en` | 1-bit | Enables PC update when high |
+| `npc` | 32-bit | Next PC value |
 
 ## Outputs
-|Name|Bits wide|
-|:---|:---:|
-|```pc```|32-bit|
-|```ins```|32-bit|
+| Name | Bits wide | Description |
+|:---|:---:|:---|
+| `pc` | 32-bit | Current program counter value |
+| `ins` | 32-bit | Instruction fetched from the Instruction Cache |
 
 ## Modules
-
 ### PC
-
 #### External IO
-
 ##### External Inputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```clk```|1-bit|
-|```rstn```|1-bit|
-|```pc_en```|1-bit|
-|```npc```|32-bit|
+| `clk` | 1-bit |
+| `rstn` | 1-bit |
+| `pc_en` | 1-bit |
+| `npc` | 32-bit |
 
 ##### External Outputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```pc```|32-bit|
+| `pc` | 32-bit |
 
 #### Internal IO
-
 ##### Internal Outputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```pc```|32-bit|
+| `pc` | 32-bit |
 
 ### Instruction Cache
-
 #### External IO
-
 ##### External Inputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```cache_clk```|1-bit|
-|```rstn_h```|1-bit|
-|```mem_response_data```|32-bit|
-|```mem_busy```|1-bit|
+| `cache_clk` | 1-bit |
+| `rstn_h` | 1-bit |
+| `mem_response_data` | 32-bit |
+| `mem_busy` | 1-bit |
 
 ##### External Outputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```ins```|32-bit|
-|```ins```|32-bit|
-|```wEn```|1-bit|
-|```rEn```|1-bit|
-|```isBurst```|1-bit|
-|```mem_address```|32-bit|
-|```mem_write_data```|32-bit|
+| `ins` | 32-bit |
+| `wEn` | 1-bit |
+| `rEn` | 1-bit |
+| `isBurst` | 1-bit |
+| `mem_address` | 32-bit |
+| `mem_write_data` | 32-bit |
 
 #### Internal IO
-
 ##### Internal Inputs
-|Name|Bits wide|
+| Name | Bits wide |
 |:---:|:---:|
-|```pc```|32-bit|
+| `pc` | 32-bit |
 
 ## Internal Connections
+| PC | Instruction Cache |
+|:---:|:---:|
+| `pc` | `pc` |
+
+## Workflows
+### PC Update Process
+- `pc_en` controls when `pc` updates.
+- If `rstn = 0`, reset `pc` to zero.
+- If `pc_en = 1`, update `pc = npc`.
+
+### Instruction Fetch Process
+- `Con_IF` sends `pc` to `Instruction Cache`.
+- If `rEn = 0`, `ins` is valid immediately (cache hit).
+- If `rEn = 1`, `Con_IF` waits for `mem_busy = 0` before using `ins` (cache miss).
+
+### Memory Access Process
+- If `Instruction Cache` needs to access memory:
+  - `rEn = 1` is asserted to request memory access.
+  - `mem_address` is assigned the requested instruction's address.
+  - `mem_busy = 1` indicates memory is still processing the request.
+- Once `mem_busy = 0`, `Instruction Cache` updates `ins`.
+- `Con_IF` receives `ins` only after `Instruction Cache` completes the memory transaction.
 
-|PC|Instruction Cache|
-|:---:|:---:|:---:|
-|```pc```|```pc```|
diff --git a/rtl/Con_IF.sv b/rtl/Con_IF.sv
new file mode 100644
index 0000000..c966acb
--- /dev/null
+++ b/rtl/Con_IF.sv
@@ -0,0 +1,41 @@
+module Con_IF (
+    input logic clk,
+    input logic cache_clk,
+    input logic rstn,
+    input logic rstn_h,
+    input logic pc_en,
+    input logic [31:0] npc,
+
+    // Memory 
+    input logic [31:0] mem_response_data, 
+    input logic mem_busy,                 
+
+    output logic [31:0] pc,
+    output logic [31:0] ins
+);
+
+    logic [31:0] mem_address;
+    logic rEn;
+    logic isBurst;
+
+    PC pc_module (
+        .clk(clk),
+        .rstn(rstn),
+        .pc_en(pc_en),
+        .npc(npc),
+        .pc(pc)
+    );
+
+    Instruction_Cache icache (
+        .cache_clk(cache_clk),
+        .rstn_h(rstn_h),
+        .mem_response_data(mem_response_data),
+        .mem_busy(mem_busy),
+        .pc(pc),           
+        .ins(ins),          
+        .rEn(rEn),         
+        .isBurst(isBurst), 
+        .mem_address(mem_address) 
+    );
+
+endmodule
diff --git a/rtl/Con_MEM.sv b/rtl/Con_MEM.sv
new file mode 100644
index 0000000..b4c5dc6
--- /dev/null
+++ b/rtl/Con_MEM.sv
@@ -0,0 +1,65 @@
+module Con_MEM (
+    input logic clk,
+    input logic rstn,
+    input logic rstn_h,
+    input logic cache_clk,
+
+    // From EX stage
+    input logic [4:0] rdn_in,
+    input logic [31:0] alu_out_in,
+    input logic [31:0] rs2d,
+
+    // Cache control signals
+    input logic dcache_en,
+    input logic dcache_rw,
+    input logic [1:0] data_mode,
+    input logic [31:0] mem_response_data,
+    input logic mem_busy,
+
+    // Outputs 
+    output logic [4:0] rdn,
+    output logic [31:0] alu_out,
+    output logic [31:0] response_data,
+    output logic wEn,
+    output logic rEn,
+    output logic isBurst,
+    output logic [31:0] mem_address,
+    output logic [31:0] mem_write_data
+);
+
+  // Intermediate wire between EXMEM and Data Cache
+  logic [31:0] mem_data;
+
+  // === Instantiate EX/MEM Latch === //
+  EXMEM exmem_inst (
+    .clk(clk),
+    .rstn(rstn),
+    .rdn_in(rdn_in),
+    .alu_out_in(alu_out_in),
+    .rs2d(rs2d),
+    .rdn(rdn),
+    .alu_out(alu_out),
+    .mem_data(mem_data)
+  );
+
+  // === Instantiate Data Cache === //
+  Conn_Data_Cache data_cache_inst (
+    .cache_clk(cache_clk),
+    .rstn_h(rstn_h),
+    .dcache_en(dcache_en),
+    .dcache_rw(dcache_rw),
+    .data_mode(data_mode),
+    .request_address(alu_out),
+    .write_data(mem_data),
+    .mem_response_data(mem_response_data),
+    .mem_busy(mem_busy),
+
+    .response_data(response_data),
+    .wEn(wEn),
+    .rEn(rEn),
+    .isBurst(isBurst),
+    .mem_address(mem_address),
+    .mem_write_data(mem_write_data)
+  );
+
+endmodule
diff --git a/rtl/Conn_Data_Cache.sv b/rtl/Conn_Data_Cache.sv
new file mode 100644
index 0000000..76dd360
--- /dev/null
+++ b/rtl/Conn_Data_Cache.sv
@@ -0,0 +1,58 @@
+module Conn_Data_Cache (
+    input logic cache_clk,
+    input logic rstn_h,
+    input logic dcache_en,
+    input logic dcache_rw,
+    input logic [1:0] data_mode,
+    input logic [31:0] request_address,
+    input logic [31:0] write_data,
+    input logic [31:0] mem_response_data,
+    input logic mem_busy,
+
+    output logic [31:0] response_data,
+    output logic wEn,
+    output logic rEn,
+    output logic isBurst,
+    output logic [31:0] mem_address,
+    output logic [31:0] mem_write_data
+);
+
+    // Internal connection wires
+    logic write_enable, read_enable, mem_ready;
+    logic mem_request, mem_write_enable;
+
+    // Instantiate Data Cache Manager
+    Data_Cache_Manager #(.WordSize(32)) manager (
+        .dcache_en(dcache_en),
+        .dcache_rw(dcache_rw),
+        .mem_request(mem_request),
+        .mem_write_enable(mem_write_enable),
+        .mem_busy(mem_busy),
+        .write_enable(write_enable),
+        .read_enable(read_enable),
+        .mem_ready(mem_ready),
+        .wEn(wEn),
+        .rEn(rEn),
+        .isBurst(isBurst)
+    );
+
+    // Instantiate L1 Data Cache
+    L1_Data_Cache cache (
+        .clk(cache_clk),
+        .rstn(rstn_h),
+        .write_enable(write_enable),
+        .read_enable(read_enable),
+        .request_address(request_address),
+        .write_data(write_data),
+        .data_mode(data_mode),
+        .response_data(response_data),
+        .mem_request(mem_request),
+        .mem_write_enable(mem_write_enable),
+        .mem_address(mem_address),
+        .mem_write_data(mem_write_data),
+        .mem_response_data(mem_response_data),
+        .mem_ready(mem_ready),
+        .c_state() // optional for debug
+    );
+
+endmodule