docs: Minor JESD204 changes

Implicit path to library when the doc is hierarchically coherent with the
library.

Signed-off-by: Jorge Marques <[email protected]>

Author: gastmaier

docs/library/jesd204/ad_ip_jesd204_tpl_adc/index.rst

@@ -4,7 +4,6 @@ ADC JESD204B/C Transport Peripheral
 ================================================================================
 
 .. hdl-component-diagram::
-   :path: library/jesd204/ad_ip_jesd204_tpl_adc
 
 The ADC JESD204B/C Transport Peripheral implements the transport level handling
 of a JESD204B/C transmitter device. It is compatible with a 
@@ -353,4 +352,4 @@ Technical Support
 
 Analog Devices will provide limited online support for anyone using the core
 with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
-:ez:`EngineerZone <fpga>`.
+:ez:`EngineerZone <fpga>`.

docs/library/jesd204/ad_ip_jesd204_tpl_dac/index.rst

@@ -4,7 +4,6 @@ DAC JESD204B/C Transport Peripheral
 ================================================================================
 
 .. hdl-component-diagram::
-   :path: library/jesd204/ad_ip_jesd204_tpl_dac
 
 The DAC JESD204B/C Transport Peripheral (AD-IP-JESD204-TRANSPORT-DAC) implements
 the transport level handling of a JESD204B/C transmitter device. It is
@@ -313,4 +312,4 @@ Technical Support
 
 Analog Devices will provide limited online support for anyone using the core
 with Analog Devices components (ADC, DAC, Video, Audio, etc) via the
-:ez:`EngineerZone <fpga>`.
+:ez:`EngineerZone <fpga>`.

docs/library/jesd204/axi_jesd204_rx/index.rst

@@ -4,7 +4,6 @@ JESD204B/C Link Receive Peripheral
 ================================================================================
 
 .. hdl-component-diagram::
-   :path: library/jesd204/axi_jesd204_rx
 
 The Analog Devices JESD204B/C Link Receive Peripheral implements the link layer
 handling of a JESD204 receive logic device. Implements the 8B/10B based link
@@ -111,7 +110,6 @@ AXI JESD204 RX Synthesis Configuration Parameters
 --------------------------------------------------------------------------------
 
 .. hdl-parameters::
-   :path: library/jesd204/axi_jesd204_rx
 
    * - ID
      - Instance identification number.
@@ -152,7 +150,6 @@ AXI JESD204 RX Signal and Interface Pins
 --------------------------------------------------------------------------------
 
 .. hdl-interfaces::
-    :path: library/jesd204/axi_jesd204_rx
 
     * - s_axi_aclk
       - All ``S_AXI`` signals and ``irq`` are synchronous to this clock.
@@ -1188,4 +1185,4 @@ encounter.
 More Information
 --------------------------------------------------------------------------------
 
--  :ref:`JESD204 High-Speed Serial Interface Support <jesd204>`
+-  :ref:`JESD204 High-Speed Serial Interface Support <jesd204>`

docs/library/jesd204/axi_jesd204_tx/index.rst

@@ -4,8 +4,6 @@ JESD204B/C Link Transmit Peripheral
 ================================================================================
 
 .. hdl-component-diagram::
-   :path: library/jesd204/axi_jesd204_tx
-
 
 The Analog Devices JESD204B/C Link Transmit Peripheral implements the link layer
 handling of a JESD204 transmit logic device. Implements the 8B/10B based link
@@ -111,7 +109,6 @@ AXI JESD204 TX Synthesis Configuration Parameters
 --------------------------------------------------------------------------------
 
 .. hdl-parameters::
-   :path: library/jesd204/axi_jesd204_tx
 
    * - ID
      - Instance identification number.
@@ -152,7 +149,6 @@ AXI JESD204 TX Signal and Interface Pins
 --------------------------------------------------------------------------------
 
 .. hdl-interfaces::
-    :path: library/jesd204/axi_jesd204_tx
 
     * - s_axi_aclk
       - All ``S_AXI`` signals and ``irq`` are synchronous to this clock.

docs/library/spi_engine/spi_engine_interconnect.rst

@@ -54,15 +54,13 @@ Signal and Interface Pins
    * - resetn
      - Synchronous active-low reset.
        Resets the internal state of the module.
-   * - s0_ctrl
+   * - s*_ctrl
      - :ref:`spi_engine control-interface` slave.
-       Connects to the first control interface master.
-   * - s1_ctrl
-     - :ref:`spi_engine control-interface` slave.
-       Connects to the second control interface master.
+       | ``s0_ctrl`` connects to the first control interface master.
+       | ``s1_ctrl`` connects to the second control interface master.
    * - m_ctrl
-     - :ref:`spi_engine control-interface` master.
-       Connects to the control interface slave.
+     - | :ref:`spi_engine control-interface` master.
+       | Connects to the control interface slave.
 
 Theory of Operation
 --------------------------------------------------------------------------------

docs/regmap/adi_regmap_xcvr.txt

@@ -1,5 +1,5 @@
 TITLE
-Xilinx XCVR (axi_xcvr) Regmap
+Xilinx XCVR (axi_xcvr)
 XCVR
 ENDTITLE
 
@@ -658,7 +658,7 @@ ENDFIELD
 ############################################################################################
 
 TITLE
-Intel XCVR (axi_xcvr) Regmap
+Intel XCVR (axi_xcvr)
 INTEL_XCVR
 ENDTITLE