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Update read/written registers for x86 unconditional jump instructions

LLVM-generated-files

X86ArchArch

Status: Open (in progress).

capstone-engine/capstonenumber 2800

#2800 In capstone-engine/capstone;

· hainest opened on Oct 14, 2025

Update read/written registers for x86 loop instructions

LLVM-generated-files

X86ArchArch

Status: Open (in progress).

capstone-engine/capstonenumber 2799

#2799 In capstone-engine/capstone;

· hainest opened on Oct 14, 2025

Refactoring the RISCV architecture to Auto-Sync on LLVM

Auto-Sync-filesAuto-SyncAuto-Sync

blockerMust be finished with the assigned milestone.Must be finished with the assigned milestone.

CS-core-filesauto-syncauto-sync

LLVM-core-filesauto-syncauto-sync

LLVM-generated-files

RISCVArchArch

Status: Open (in progress).

capstone-engine/capstonenumber 2756

#2756 In capstone-engine/capstone;

· moste00 opened on Jul 16, 2025

· 

v6 - Beta

initial implementation of the Sail-generated RISCV disassembler module

LLVM-generated-files

RISCVArchArch

Status: Draft (not ready).

capstone-engine/capstonenumber 2498

#2498 In capstone-engine/capstone;

· moste00 opened on Oct 4, 2024