diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 5300bcf55a1..71fbb5d19c7 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -858,7 +858,12 @@ package experimental {
     private[chisel3] def createSecretIO[A <: Data](data: => A)(implicit sourceInfo: SourceInfo): A = {
       val iodef = data
       requireIsChiselType(iodef, "io type")
-      require(!isFullyClosed, "Cannot create secret ports if module is fully closed")
+      if (isFullyClosed)
+        Builder.error(s"Cannot bore or tap into fully closed ${this.name} (from ${Builder.currentModule.get.name})")
+      if (!isIOCreationAllowed)
+        Builder.error(
+          s"Cannot bore or tap into ${this.name} (from ${Builder.currentModule.get.name}) if IO creation is not allowed"
+        )
 
       Module.assignCompatDir(iodef)
       iodef.bind(SecretPortBinding(this), iodef.specifiedDirection)
diff --git a/src/test/scala-2/chiselTests/BoringUtilsSpec.scala b/src/test/scala-2/chiselTests/BoringUtilsSpec.scala
index 3ea09091be5..044c3969ab3 100644
--- a/src/test/scala-2/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala-2/chiselTests/BoringUtilsSpec.scala
@@ -689,4 +689,21 @@ class BoringUtilsSpec extends AnyFlatSpec with Matchers with LogUtils with FileC
            |""".stripMargin
       )
   }
+  it should "fail if endIOCreation is set" in {
+
+    class Bar extends RawModule {
+      val baz = Module(new Baz)
+      BoringUtils.bore(baz.c)
+    }
+
+    class Baz extends RawModule {
+      val c = Wire(Property[Int]())
+      endIOCreation()
+    }
+
+    val e = intercept[Exception] {
+      circt.stage.ChiselStage.emitCHIRRTL(new Bar, args)
+    }
+    e.getMessage should include("Cannot bore or tap into Baz (from Bar) if IO creation is not allowed")
+  }
 }