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kelpsyberrykelpsyberry
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Remove generic_const_exprs and update nightly
1 parent a946754 commit dfac8e7

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35 files changed

+1552
-1047
lines changed

35 files changed

+1552
-1047
lines changed

‎Cargo.lock‎

Lines changed: 947 additions & 567 deletions
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‎core/build.rs‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -156,8 +156,8 @@ mod interpreter {
156156
),
157157
WbOff::Imm => write!(
158158
file,
159-
"{}{}::<{{WbOffTy::Imm}}, {}, {{WbAddressing::{}}}>",
160-
load_store, word_byte, offset_upwards, addressing
159+
"{load_store}{word_byte}::<{{WbOffTy::Imm}}, {offset_upwards}, \
160+
{{WbAddressing::{addressing}}}>"
161161
),
162162
}
163163
}
@@ -841,15 +841,15 @@ mod disasm {
841841
} => {
842842
write!(
843843
file,
844-
"load_store_misc::<{}, \"{}\", {}, {}, {{MiscAddressing::{}}}>",
844+
"load_store_misc::<{}, {{{}}}, {}, {}, {{MiscAddressing::{}}}>",
845845
!matches!(ty, MiscTransferTy::Strh | MiscTransferTy::Strd),
846846
match ty {
847-
MiscTransferTy::Ldrh => "h",
848-
MiscTransferTy::Strh => "h",
849-
MiscTransferTy::Ldrd => "d",
850-
MiscTransferTy::Strd => "d",
851-
MiscTransferTy::Ldrsb => "sb",
852-
MiscTransferTy::Ldrsh => "sh",
847+
MiscTransferTy::Ldrh => "LoadStoreMiscTy::Half",
848+
MiscTransferTy::Strh => "LoadStoreMiscTy::Half",
849+
MiscTransferTy::Ldrd => "LoadStoreMiscTy::Double",
850+
MiscTransferTy::Strd => "LoadStoreMiscTy::Double",
851+
MiscTransferTy::Ldrsb => "LoadStoreMiscTy::SignedByte",
852+
MiscTransferTy::Ldrsh => "LoadStoreMiscTy::SignedHalf",
853853
},
854854
offset_imm,
855855
offset_upwards,
@@ -1010,10 +1010,10 @@ mod disasm {
10101010
write!(file, "ldr_pc_rel")
10111011
}
10121012
Instr::LoadStoreReg { ty, offset_reg: _ } => {
1013-
let name = [
1014-
"str", "strh", "strb", "ldrsb", "ldr", "ldrh", "ldrb", "ldrsh",
1013+
let ty = [
1014+
"Str", "Strh", "Strb", "Ldrsb", "Ldr", "Ldrh", "Ldrb", "Ldrsh",
10151015
][ty as usize];
1016-
write!(file, "ldr_str::<\"{name}\", 0, false>")
1016+
write!(file, "ldr_str::<{{ThumbLoadStoreTy::{ty}}}, 0, false>")
10171017
}
10181018
Instr::LoadStoreWbImm {
10191019
byte,
@@ -1022,17 +1022,17 @@ mod disasm {
10221022
} => {
10231023
write!(
10241024
file,
1025-
"ldr_str::<\"{}{}\", {}, true>",
1026-
if load { "ldr" } else { "str" },
1025+
"ldr_str::<{{ThumbLoadStoreTy::{}{}}}, {}, true>",
1026+
if load { "Ldr" } else { "Str" },
10271027
if byte { "b" } else { "" },
10281028
if byte { 0 } else { 2 },
10291029
)
10301030
}
10311031
Instr::LoadStoreHalfImm { load, offset: _ } => {
10321032
write!(
10331033
file,
1034-
"ldr_str::<\"{}h\", 1, true>",
1035-
if load { "ldr" } else { "str" }
1034+
"ldr_str::<{{ThumbLoadStoreTy::{}h}}, 1, true>",
1035+
if load { "Ldr" } else { "Str" }
10361036
)
10371037
}
10381038
Instr::LoadStoreStack { load, reg: _ } => {

‎core/src/cpu/disasm/arm.rs‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,10 @@ mod other;
88
use other::*;
99

1010
use super::{
11-
common::{DpOpTy, DpOperand, MiscAddressing, ShiftTy, WbAddressing, WbOffTy, COND_STRINGS},
11+
common::{
12+
DpOpTy, DpOperand, LoadStoreMiscTy, MiscAddressing, ShiftTy, WbAddressing, WbOffTy,
13+
COND_STRINGS,
14+
},
1215
Context,
1316
};
1417

‎core/src/cpu/disasm/arm/mem.rs‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
use super::super::{
2-
common::{MiscAddressing, ShiftTy, WbAddressing, WbOffTy},
2+
common::{LoadStoreMiscTy, MiscAddressing, ShiftTy, WbAddressing, WbOffTy},
33
Context,
44
};
55
use core::fmt::Write;
@@ -74,7 +74,7 @@ pub(super) fn load_store_wb<
7474

7575
pub(super) fn load_store_misc<
7676
const LOAD: bool,
77-
const SUFFIX: &'static str,
77+
const TY: LoadStoreMiscTy,
7878
const OFF_IMM: bool,
7979
const UPWARDS: bool,
8080
const ADDRESSING: MiscAddressing,
@@ -86,8 +86,14 @@ pub(super) fn load_store_misc<
8686
let src_dst_reg = instr >> 12 & 0xF;
8787
let base_reg = instr >> 16 & 0xF;
8888
ctx.next_instr.opcode = format!(
89-
"{}{cond}{SUFFIX} r{src_dst_reg}, [r{base_reg}",
89+
"{}{cond}{} r{src_dst_reg}, [r{base_reg}",
9090
if LOAD { "ldr" } else { "str" },
91+
match TY {
92+
LoadStoreMiscTy::Half => "h",
93+
LoadStoreMiscTy::Double => "d",
94+
LoadStoreMiscTy::SignedByte => "sb",
95+
LoadStoreMiscTy::SignedHalf => "sh",
96+
}
9197
);
9298
if !ADDRESSING.preincrement() {
9399
ctx.next_instr.opcode.push(']');
@@ -111,7 +117,7 @@ pub(super) fn load_store_misc<
111117
if src_dst_reg == 15
112118
|| (!OFF_IMM && instr & 0xF00 != 0)
113119
|| (ADDRESSING.writeback() && (base_reg == src_dst_reg || base_reg == 15))
114-
|| (SUFFIX == "d" && src_dst_reg & 1 != 0)
120+
|| (TY == LoadStoreMiscTy::Double && src_dst_reg & 1 != 0)
115121
{
116122
"Unpredictable".clone_into(&mut ctx.next_instr.comment);
117123
}

‎core/src/cpu/disasm/common.rs‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,23 @@ pub enum DpOpSpecialTy {
1212
Cmp,
1313
Mov,
1414
}
15+
16+
#[derive(Clone, Copy, PartialEq, Eq, ConstParamTy, Debug)]
17+
pub enum LoadStoreMiscTy {
18+
Half,
19+
Double,
20+
SignedByte,
21+
SignedHalf,
22+
}
23+
24+
#[derive(Clone, Copy, PartialEq, Eq, ConstParamTy, Debug)]
25+
pub enum ThumbLoadStoreTy {
26+
Str,
27+
Strh,
28+
Strb,
29+
Ldrsb,
30+
Ldr,
31+
Ldrh,
32+
Ldrb,
33+
Ldrsh,
34+
}

‎core/src/cpu/disasm/thumb.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ mod other;
88
use other::*;
99

1010
use super::{
11-
common::{DpOpImm8Ty, DpOpRegTy, DpOpSpecialTy, ShiftImmTy},
11+
common::{DpOpImm8Ty, DpOpRegTy, DpOpSpecialTy, ShiftImmTy, ThumbLoadStoreTy},
1212
Context,
1313
};
1414

‎core/src/cpu/disasm/thumb/mem.rs‎

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,33 @@
1-
use super::super::Context;
1+
use super::super::{common::ThumbLoadStoreTy, Context};
22
use core::fmt::Write;
33

4-
pub(super) fn ldr_str<const OPCODE: &'static str, const IMM_OFFSET_SHIFT: u8, const IMM: bool>(
4+
pub(super) fn ldr_str<
5+
const TY: ThumbLoadStoreTy,
6+
const IMM_OFFSET_SHIFT: u8,
7+
const IMM: bool,
8+
>(
59
ctx: &mut Context,
610
instr: u16,
711
) {
812
ctx.branch_addr_base = None;
913
let src_dst_reg = instr & 7;
1014
let base_reg = instr >> 3 & 7;
15+
let opcode = match TY {
16+
ThumbLoadStoreTy::Str => "str",
17+
ThumbLoadStoreTy::Strh => "strh",
18+
ThumbLoadStoreTy::Strb => "strb",
19+
ThumbLoadStoreTy::Ldrsb => "ldrsb",
20+
ThumbLoadStoreTy::Ldr => "ldr",
21+
ThumbLoadStoreTy::Ldrh => "ldrh",
22+
ThumbLoadStoreTy::Ldrb => "ldrb",
23+
ThumbLoadStoreTy::Ldrsh => "ldrsh",
24+
};
1125
ctx.next_instr.opcode = if IMM {
1226
let offset = (instr >> 6 & 0x1F) << IMM_OFFSET_SHIFT;
13-
format!("{OPCODE} r{src_dst_reg}, [r{base_reg}, #{offset:#04X}]")
27+
format!("{opcode} r{src_dst_reg}, [r{base_reg}, #{offset:#04X}]")
1428
} else {
1529
let off_reg = instr >> 6 & 7;
16-
format!("{OPCODE} r{src_dst_reg}, [r{base_reg}, r{off_reg}]")
30+
format!("{opcode} r{src_dst_reg}, [r{base_reg}, r{off_reg}]")
1731
};
1832
}
1933

‎core/src/cpu/interpreter/arm7.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -714,7 +714,7 @@ impl Arm7Data for EngineData {
714714
let instr = bus::read_32::<CpuAccess, _>(emu, addr);
715715
emu.arm7.engine_data.prefetch_nseq = false;
716716
arm::handle_instr(emu, instr);
717-
};
717+
}
718718
}
719719
}
720720
}

‎core/src/dldi.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ pub(crate) fn handle_call_instr_function<E: Engine, const ARM9: bool>(
141141
for sector in start_sector..start_sector + sectors {
142142
if !dldi.provider.read_sector(sector, &mut dldi.buffer) {
143143
break 'outer false;
144-
};
144+
}
145145
if dst_addr & 3 == 0 {
146146
for i in (0..0x200).step_by(4) {
147147
(if ARM9 {
@@ -194,7 +194,7 @@ pub(crate) fn handle_call_instr_function<E: Engine, const ARM9: bool>(
194194
src_addr += 0x200;
195195
if !dldi.provider.write_sector(sector, &dldi.buffer) {
196196
break 'outer false;
197-
};
197+
}
198198
}
199199
true
200200
}

‎core/src/gpu/engine_3d.rs‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,7 +1076,7 @@ impl Engine3d {
10761076
// - Assumes that shared_verts_len == 0 or 2
10771077
// - Assumes that verts.len() == 3 or 4
10781078
// - Assumes that the clipped vertices will not exceed 10 (guaranteed geometrically)
1079-
let mut buffer_1 = MaybeUninit::uninit_array::<10>();
1079+
let mut buffer_1 = [MaybeUninit::uninit(); 10];
10801080
unsafe {
10811081
for i in 0..shared_verts_len {
10821082
*clip_buffer.get_unchecked_mut(i) = MaybeUninit::new(*verts.get_unchecked(i));
@@ -1107,7 +1107,7 @@ impl Engine3d {
11071107
}
11081108

11091109
let shared_verts_len = (self.connect_to_last_strip_prim as usize) << 1;
1110-
let mut clip_buffer = MaybeUninit::uninit_array::<10>();
1110+
let mut clip_buffer = [MaybeUninit::uninit(); 10];
11111111
let Some((clipped_verts_len, clipped)) = self.clip_polygon(
11121112
&self.cur_prim_verts[..self.cur_prim_max_verts.get() as usize],
11131113
shared_verts_len,
@@ -1116,9 +1116,8 @@ impl Engine3d {
11161116
self.connect_to_last_strip_prim = false;
11171117
return;
11181118
};
1119-
let clipped_verts = unsafe {
1120-
MaybeUninit::slice_assume_init_mut(&mut clip_buffer[..clipped_verts_len.get() as usize])
1121-
};
1119+
let clipped_verts =
1120+
unsafe { clip_buffer[..clipped_verts_len.get() as usize].assume_init_mut() };
11221121

11231122
if self.vert_ram_level as usize
11241123
> self.vert_ram.len() - (clipped_verts_len.get() as usize - shared_verts_len)
@@ -1314,7 +1313,7 @@ impl Engine3d {
13141313
}
13151314
}
13161315

1317-
let mut clip_buffer = MaybeUninit::uninit_array::<10>();
1316+
let mut clip_buffer = [MaybeUninit::uninit(); 10];
13181317

13191318
for x in 0..2 {
13201319
if self

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