From 3ea3709599466826bbb7835d80a4b8a6ea47bcae Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9s=20Manelli?= <andresmanelli@gmail.com>
Date: Thu, 11 Jul 2019 21:52:46 +0200
Subject: [PATCH 01/24] Add entity parsing

---
 hdlparse/vhdl_parser.py | 43 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 6adb021..db785a2 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -84,7 +84,9 @@
     (r'--.*\n', None),
   ],
   'entity': [
-    (r'end\s+entity\s*;', 'end_entity', '#pop'),
+    (r'generic\s*\(', None, 'generic_list'),
+    (r'port\s*\(', None, 'port_list'),
+    (r'end\s+\w+\s*;', 'end_entity', '#pop'),
     (r'/\*', 'block_comment', 'block_comment'),
     (r'--.*\n', None),
   ],
@@ -290,6 +292,30 @@ def __init__(self, name, package, parameters, desc=None):
   def __repr__(self):
     return "VhdlProcedure('{}')".format(self.name)
 
+class VhdlEntity(VhdlObject):
+  '''Entity declaration
+
+  Args:
+    name (str): Name of the entity
+    ports (list of VhdlParameter): Port parameters to the entity
+    generics (list of VhdlParameter): Generic parameters to the entity
+    sections (list of str): Metacomment sections
+    desc (str, optional): Description from object metacomments
+  '''
+  def __init__(self, name, ports, generics=None, sections=None, desc=None):
+    VhdlObject.__init__(self, name, desc)
+    self.kind = 'entity'
+    self.generics = generics if generics is not None else []
+    self.ports = ports
+    self.sections = sections if sections is not None else {}
+
+  def __repr__(self):
+    return "VhdlEntity('{}')".format(self.name)
+
+  def dump(self):
+    print('VHDL entity: {}'.format(self.name))
+    for p in self.ports:
+      print('\t{} ({}), {} ({})'.format(p.name, type(p.name), p.data_type, type(p.data_type)))
 
 class VhdlComponent(VhdlObject):
   '''Component declaration
@@ -423,6 +449,15 @@ def parse_vhdl(text):
       kind = None
       name = None
 
+    elif action == 'entity':
+      kind = 'entity'
+      name = groups[0]
+      generics = []
+      ports = []
+      param_items = []
+      sections = []
+      port_param_index = 0
+
     elif action == 'component':
       kind = 'component'
       name = groups[0]
@@ -469,6 +504,12 @@ def parse_vhdl(text):
       param_items = []
       last_item = ports[-1]
 
+    elif action == 'end_entity':
+      vobj = VhdlEntity(name, ports, generics, dict(sections), metacomments)
+      objects.append(vobj)
+      last_item = None
+      metacomments = []
+
     elif action == 'end_component':
       vobj = VhdlComponent(name, cur_package, ports, generics, dict(sections), metacomments)
       objects.append(vobj)

From 21b54a6f158ce761d90a1199317ff3ac456a7e27 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9s=20Manelli?= <andresmanelli@gmail.com>
Date: Thu, 11 Jul 2019 22:31:30 +0200
Subject: [PATCH 02/24] Add default values for ports and generics

---
 hdlparse/vhdl_parser.py | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index db785a2..747eae3 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -478,6 +478,9 @@ def parse_vhdl(text):
       param_items = []
       last_item = generics[-1]
 
+    elif action == 'generic_param_default':
+      last_item.default_value = groups[0]
+
     elif action == 'port_param':
       param_items.append(groups[0])
       port_param_index += 1
@@ -491,6 +494,9 @@ def parse_vhdl(text):
       param_items = []
       last_item = ports[-1]
 
+    elif action == 'port_param_default':
+      last_item.default_value = groups[0]
+
     elif action == 'port_array_param_type':
       mode, ptype = groups
       array_range_start_pos = pos[1]

From 1ed74979f708af8efd1e2b2e9c0a84b0596b2dbb Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 11:57:47 +0100
Subject: [PATCH 03/24] Add line comments to port definitions

---
 hdlparse/vhdl_parser.py | 54 ++++++++++++++++++++++++++---------------
 1 file changed, 35 insertions(+), 19 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 747eae3..575e2ee 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -119,17 +119,17 @@
     (r'--#\s*{{(.*)}}\n', 'section_meta'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
-    (r'--.*\n', None),
+    (r'--(.*)\n', 'line_comment'),
   ],
   'port_param_type': [
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*\(', 'port_array_param_type', 'array_range'),
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*', 'port_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'port_param_default'),
+    (r'--(.*)\n', 'line_comment'),
     (r'\)\s*;', 'end_port', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
-    (r'--.*\n', None),
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
@@ -175,6 +175,7 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non
     self.data_type = data_type
     self.default_value = default_value
     self.desc = desc
+    self.param_desc = None
 
   def __str__(self):
     if self.mode is not None:
@@ -183,6 +184,8 @@ def __str__(self):
       param = '{} : {}'.format(self.name, self.data_type)
     if self.default_value is not None:
       param = '{} := {}'.format(param, self.default_value)
+    if self.param_desc is not None:
+      param = '{} --{}'.format(param, self.param_desc)
     return param
       
   def __repr__(self):
@@ -294,7 +297,6 @@ def __repr__(self):
 
 class VhdlEntity(VhdlObject):
   '''Entity declaration
-
   Args:
     name (str): Name of the entity
     ports (list of VhdlParameter): Port parameters to the entity
@@ -381,7 +383,7 @@ def parse_vhdl(text):
   ports = []
   sections = []
   port_param_index = 0
-  last_item = None
+  last_items = []
   array_range_start_pos = 0
 
   objects = []
@@ -389,10 +391,11 @@ def parse_vhdl(text):
   for pos, action, groups in lex.run(text):
     if action == 'metacomment':
       realigned = re.sub(r'^#+', lambda m: ' ' * len(m.group(0)), groups[0])
-      if last_item is None:
+      if not last_items:
         metacomments.append(realigned)
       else:
-        last_item.desc = realigned
+        for i in last_items:
+          i.desc = realigned
     if action == 'section_meta':
       sections.append((port_param_index, groups[0]))
 
@@ -448,7 +451,7 @@ def parse_vhdl(text):
       param_items = []
       kind = None
       name = None
-
+   
     elif action == 'entity':
       kind = 'entity'
       name = groups[0]
@@ -473,13 +476,17 @@ def parse_vhdl(text):
     elif action == 'generic_param_type':
       ptype = groups[0]
       
+      last_items = []
       for i in param_items:
-        generics.append(VhdlParameter(i, 'in', ptype))
+        p = VhdlParameter(i, 'in', ptype)
+        generics.append(p)
+        last_items.append(p)
+
       param_items = []
-      last_item = generics[-1]
 
     elif action == 'generic_param_default':
-      last_item.default_value = groups[0]
+      for i in last_items:
+        i.default_value = groups[0]
 
     elif action == 'port_param':
       param_items.append(groups[0])
@@ -488,14 +495,17 @@ def parse_vhdl(text):
     elif action == 'port_param_type':
       mode, ptype = groups
 
+      last_items = []
       for i in param_items:
-        ports.append(VhdlParameter(i, mode, ptype))
+        p = VhdlParameter(i, mode, ptype)
+        ports.append(p)
+        last_items.append(p)
 
       param_items = []
-      last_item = ports[-1]
 
     elif action == 'port_param_default':
-      last_item.default_value = groups[0]
+      for i in last_items:
+        i.default_value = groups[0]
 
     elif action == 'port_array_param_type':
       mode, ptype = groups
@@ -504,22 +514,24 @@ def parse_vhdl(text):
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
+      last_items = []
       for i in param_items:
-        ports.append(VhdlParameter(i, mode, ptype + arange))
+        p = VhdlParameter(i, mode, ptype + arange)
+        ports.append(p)
+        last_items.append(p)
 
       param_items = []
-      last_item = ports[-1]
 
     elif action == 'end_entity':
       vobj = VhdlEntity(name, ports, generics, dict(sections), metacomments)
       objects.append(vobj)
-      last_item = None
+      last_items = []
       metacomments = []
 
     elif action == 'end_component':
       vobj = VhdlComponent(name, cur_package, ports, generics, dict(sections), metacomments)
       objects.append(vobj)
-      last_item = None
+      last_items = []
       metacomments = []
 
     elif action == 'package':
@@ -552,6 +564,10 @@ def parse_vhdl(text):
       name = None
       metacomments = []
 
+    elif action == 'line_comment':
+      for i in last_items:
+        i.param_desc = groups[0]
+
   return objects
 
 
@@ -757,8 +773,8 @@ def register_array_types_from_sources(self, source_files):
 
   component acomp is
     port (
-      a,b,c : in std_ulogic;
-      f,g,h : inout bit
+      a,b,c : in std_ulogic;   -- no default value
+      f,g,h : inout bit := '1' -- default value '1'
     );
   end component;
 

From a084521d199ba54316ce59dd31e7e330dc2ffe9d Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 15:52:14 +0100
Subject: [PATCH 04/24] Destinguish between line comments for ports of the same
 type and for the whole port list

---
 hdlparse/vhdl_parser.py | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 575e2ee..0aa7751 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -104,9 +104,12 @@
     (r'--.*\n', None),
   ],
   'generic_param_type': [
-    (r'\s*(\w+)\s*', 'generic_param_type'),
+    (r'\s*(\w+)[ \t\r\f\v]*', 'generic_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'generic_param_default'),
+    (r'\)\s*;\s*--(.*)\n', 'line_comment', '#pop:2'),
+    (r'\n\s*\)\s*;\s*--(.*)\n', 'generic_list_comment', '#pop:2'),
+    (r'\n\s*', None),
     (r'\)\s*;', 'end_generic', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
@@ -123,10 +126,13 @@
   ],
   'port_param_type': [
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*\(', 'port_array_param_type', 'array_range'),
-    (r'\s*(in|out|inout|buffer)\s+(\w+)\s*', 'port_param_type'),
+    (r'\s*(in|out|inout|buffer)\s+(\w+)[ \t\r\f\v]*', 'port_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'port_param_default'),
     (r'--(.*)\n', 'line_comment'),
+    (r'\)\s*;\s*--(.*)\n', 'line_comment', '#pop:2'),
+    (r'\n\s*\)\s*;\s*--(.*)\n', 'port_list_comment', '#pop:2'),
+    (r'\n\s*', None),
     (r'\)\s*;', 'end_port', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
@@ -566,7 +572,8 @@ def parse_vhdl(text):
 
     elif action == 'line_comment':
       for i in last_items:
-        i.param_desc = groups[0]
+        if not i.param_desc:
+          i.param_desc = groups[0]
 
   return objects
 
@@ -774,8 +781,9 @@ def register_array_types_from_sources(self, source_files):
   component acomp is
     port (
       a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- default value '1'
-    );
+      f,g,h : inout bit := '1' -- bit ports 
+    ); -- port list comment
+    
   end component;
 
 end package;

From 8a6530dcca8457d947f740743e8e9fa05097f5c2 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 16:00:04 +0100
Subject: [PATCH 05/24] Make it Python3 friendly

---
 hdlparse/minilexer.py   | 4 ++--
 hdlparse/vhdl_parser.py | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hdlparse/minilexer.py b/hdlparse/minilexer.py
index 30121ae..bb6d14b 100644
--- a/hdlparse/minilexer.py
+++ b/hdlparse/minilexer.py
@@ -22,7 +22,7 @@ def __init__(self, tokens, flags=re.MULTILINE):
     self.tokens = {}
 
     # Pre-process the state definitions
-    for state, patterns in tokens.iteritems():
+    for state, patterns in tokens.items():
       full_patterns = []
       for p in patterns:
         pat = re.compile(p[0], flags)
@@ -33,7 +33,7 @@ def __init__(self, tokens, flags=re.MULTILINE):
         if new_state and new_state.startswith('#pop'):
           try:
             new_state = -int(new_state.split(':')[1])
-          except IndexError, ValueError:
+          except (IndexError, ValueError):
             new_state = -1
 
         full_patterns.append((pat, action, new_state))
diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 0aa7751..87c733c 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -753,7 +753,7 @@ def _register_array_types(self, objects):
     subtypes = {o.name:o.base_type for o in objects if isinstance(o, VhdlSubtype)}
 
     # Find all subtypes of an array type
-    for k,v in subtypes.iteritems():
+    for k,v in subtypes.items():
       while v in subtypes: # Follow subtypes of subtypes
         v = subtypes[v]
       if v in self.array_types:

From 1b30856180032b5ca75f1d024be7e3d474819299 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 16:19:52 +0100
Subject: [PATCH 06/24] Add comment for param_desc attribute of class
 VhdlParameter

---
 hdlparse/vhdl_parser.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 87c733c..731577d 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -174,8 +174,9 @@ class VhdlParameter(object):
     data_type (str): Type name for the parameter
     default_value (str): Default value of the parameter
     desc (str): Description from object metacomments
+    param_desc (str): Description of the parameter
   '''
-  def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None):
+  def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None, param_desc = None):
     self.name = name
     self.mode = mode
     self.data_type = data_type

From 3ad47d94258a6667049b7cbdf3de8e2f37ad7777 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Tue, 28 Jul 2020 16:59:14 +0200
Subject: [PATCH 07/24] Add VhdlParameterType class to support vector and array
 parameter types

---
 hdlparse/vhdl_parser.py | 37 +++++++++++++++++++++++++++++++------
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 731577d..ec80ef5 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -139,10 +139,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [
@@ -186,9 +188,9 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non
 
   def __str__(self):
     if self.mode is not None:
-      param = '{} : {} {}'.format(self.name, self.mode, self.data_type)
+      param = '{} : {} {}'.format(self.name, self.mode, self.data_type.name + self.data_type.arange)
     else:
-      param = '{} : {}'.format(self.name, self.data_type)
+      param = '{} : {}'.format(self.name, self.data_type.name + self.data_type.arange)
     if self.default_value is not None:
       param = '{} := {}'.format(param, self.default_value)
     if self.param_desc is not None:
@@ -196,7 +198,27 @@ def __str__(self):
     return param
       
   def __repr__(self):
-    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type)
+    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type.name + self.data_type.arange)
+
+class VhdlParameterType(object):
+  '''Parameter type definition
+
+  Args:  
+    name (str): Name of the type
+    direction(str): "to" or "downto"
+    msb (str): A digit or a name
+    lsb (str): A digit or a name
+    arange (str): Original array range string
+  '''
+  def __init__(self, name, direction = "", msb = "", lsb = "", arange = ""):
+    self.name = name
+    self.direction = direction.strip()
+    self.msb = msb.strip()
+    self.lsb = lsb.strip()
+    self.arange = arange
+
+  def __repr__(self):
+    return "VhdlParameterType('{}','{}')".format(self.name, self.arange)
 
 class VhdlPackage(VhdlObject):
   '''Package declaration
@@ -485,7 +507,7 @@ def parse_vhdl(text):
       
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, 'in', ptype)
+        p = VhdlParameter(i, 'in', VhdlParameterType(ptype))
         generics.append(p)
         last_items.append(p)
 
@@ -504,7 +526,7 @@ def parse_vhdl(text):
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype))
         ports.append(p)
         last_items.append(p)
 
@@ -518,12 +540,15 @@ def parse_vhdl(text):
       mode, ptype = groups
       array_range_start_pos = pos[1]
 
+    elif action == 'array_range_val':
+      msb, direction, lsb = groups
+
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype + arange)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, msb, lsb, arange))
         ports.append(p)
         last_items.append(p)
 

From 2350416b64e37c27cb3d92c0e5ed7d54665a38dd Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Mon, 7 Dec 2020 14:53:11 +0100
Subject: [PATCH 08/24] Support end entity with entity keyword and name

---
 hdlparse/vhdl_parser.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 731577d..b970c6e 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -87,6 +87,7 @@
     (r'generic\s*\(', None, 'generic_list'),
     (r'port\s*\(', None, 'port_list'),
     (r'end\s+\w+\s*;', 'end_entity', '#pop'),
+    (r'end\s+entity\s+\w+\s*;', 'end_entity', '#pop'),
     (r'/\*', 'block_comment', 'block_comment'),
     (r'--.*\n', None),
   ],

From fc4901611cabb242751d1c12c07076ee293ba589 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Mon, 7 Dec 2020 15:26:56 +0100
Subject: [PATCH 09/24] Improve pattern for array_range_val

---
 hdlparse/vhdl_parser.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 49b47bc..80c6c06 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,12 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [

From e57858fb3947e01a621968ce6c6656acea3eda34 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 11:57:47 +0100
Subject: [PATCH 10/24] Add line comments to port definitions

---
 hdlparse/vhdl_parser.py | 54 ++++++++++++++++++++++++++---------------
 1 file changed, 35 insertions(+), 19 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 747eae3..575e2ee 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -119,17 +119,17 @@
     (r'--#\s*{{(.*)}}\n', 'section_meta'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
-    (r'--.*\n', None),
+    (r'--(.*)\n', 'line_comment'),
   ],
   'port_param_type': [
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*\(', 'port_array_param_type', 'array_range'),
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*', 'port_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'port_param_default'),
+    (r'--(.*)\n', 'line_comment'),
     (r'\)\s*;', 'end_port', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
-    (r'--.*\n', None),
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
@@ -175,6 +175,7 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non
     self.data_type = data_type
     self.default_value = default_value
     self.desc = desc
+    self.param_desc = None
 
   def __str__(self):
     if self.mode is not None:
@@ -183,6 +184,8 @@ def __str__(self):
       param = '{} : {}'.format(self.name, self.data_type)
     if self.default_value is not None:
       param = '{} := {}'.format(param, self.default_value)
+    if self.param_desc is not None:
+      param = '{} --{}'.format(param, self.param_desc)
     return param
       
   def __repr__(self):
@@ -294,7 +297,6 @@ def __repr__(self):
 
 class VhdlEntity(VhdlObject):
   '''Entity declaration
-
   Args:
     name (str): Name of the entity
     ports (list of VhdlParameter): Port parameters to the entity
@@ -381,7 +383,7 @@ def parse_vhdl(text):
   ports = []
   sections = []
   port_param_index = 0
-  last_item = None
+  last_items = []
   array_range_start_pos = 0
 
   objects = []
@@ -389,10 +391,11 @@ def parse_vhdl(text):
   for pos, action, groups in lex.run(text):
     if action == 'metacomment':
       realigned = re.sub(r'^#+', lambda m: ' ' * len(m.group(0)), groups[0])
-      if last_item is None:
+      if not last_items:
         metacomments.append(realigned)
       else:
-        last_item.desc = realigned
+        for i in last_items:
+          i.desc = realigned
     if action == 'section_meta':
       sections.append((port_param_index, groups[0]))
 
@@ -448,7 +451,7 @@ def parse_vhdl(text):
       param_items = []
       kind = None
       name = None
-
+   
     elif action == 'entity':
       kind = 'entity'
       name = groups[0]
@@ -473,13 +476,17 @@ def parse_vhdl(text):
     elif action == 'generic_param_type':
       ptype = groups[0]
       
+      last_items = []
       for i in param_items:
-        generics.append(VhdlParameter(i, 'in', ptype))
+        p = VhdlParameter(i, 'in', ptype)
+        generics.append(p)
+        last_items.append(p)
+
       param_items = []
-      last_item = generics[-1]
 
     elif action == 'generic_param_default':
-      last_item.default_value = groups[0]
+      for i in last_items:
+        i.default_value = groups[0]
 
     elif action == 'port_param':
       param_items.append(groups[0])
@@ -488,14 +495,17 @@ def parse_vhdl(text):
     elif action == 'port_param_type':
       mode, ptype = groups
 
+      last_items = []
       for i in param_items:
-        ports.append(VhdlParameter(i, mode, ptype))
+        p = VhdlParameter(i, mode, ptype)
+        ports.append(p)
+        last_items.append(p)
 
       param_items = []
-      last_item = ports[-1]
 
     elif action == 'port_param_default':
-      last_item.default_value = groups[0]
+      for i in last_items:
+        i.default_value = groups[0]
 
     elif action == 'port_array_param_type':
       mode, ptype = groups
@@ -504,22 +514,24 @@ def parse_vhdl(text):
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
+      last_items = []
       for i in param_items:
-        ports.append(VhdlParameter(i, mode, ptype + arange))
+        p = VhdlParameter(i, mode, ptype + arange)
+        ports.append(p)
+        last_items.append(p)
 
       param_items = []
-      last_item = ports[-1]
 
     elif action == 'end_entity':
       vobj = VhdlEntity(name, ports, generics, dict(sections), metacomments)
       objects.append(vobj)
-      last_item = None
+      last_items = []
       metacomments = []
 
     elif action == 'end_component':
       vobj = VhdlComponent(name, cur_package, ports, generics, dict(sections), metacomments)
       objects.append(vobj)
-      last_item = None
+      last_items = []
       metacomments = []
 
     elif action == 'package':
@@ -552,6 +564,10 @@ def parse_vhdl(text):
       name = None
       metacomments = []
 
+    elif action == 'line_comment':
+      for i in last_items:
+        i.param_desc = groups[0]
+
   return objects
 
 
@@ -757,8 +773,8 @@ def register_array_types_from_sources(self, source_files):
 
   component acomp is
     port (
-      a,b,c : in std_ulogic;
-      f,g,h : inout bit
+      a,b,c : in std_ulogic;   -- no default value
+      f,g,h : inout bit := '1' -- default value '1'
     );
   end component;
 

From c5cf5941b8fbada3cc12fa1b8aac1f5cb260fb41 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 15:52:14 +0100
Subject: [PATCH 11/24] Destinguish between line comments for ports of the same
 type and for the whole port list

---
 hdlparse/vhdl_parser.py | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 575e2ee..0aa7751 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -104,9 +104,12 @@
     (r'--.*\n', None),
   ],
   'generic_param_type': [
-    (r'\s*(\w+)\s*', 'generic_param_type'),
+    (r'\s*(\w+)[ \t\r\f\v]*', 'generic_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'generic_param_default'),
+    (r'\)\s*;\s*--(.*)\n', 'line_comment', '#pop:2'),
+    (r'\n\s*\)\s*;\s*--(.*)\n', 'generic_list_comment', '#pop:2'),
+    (r'\n\s*', None),
     (r'\)\s*;', 'end_generic', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
@@ -123,10 +126,13 @@
   ],
   'port_param_type': [
     (r'\s*(in|out|inout|buffer)\s+(\w+)\s*\(', 'port_array_param_type', 'array_range'),
-    (r'\s*(in|out|inout|buffer)\s+(\w+)\s*', 'port_param_type'),
+    (r'\s*(in|out|inout|buffer)\s+(\w+)[ \t\r\f\v]*', 'port_param_type'),
     (r'\s*;\s*', None, '#pop'),
     (r"\s*:=\s*([\w']+)", 'port_param_default'),
     (r'--(.*)\n', 'line_comment'),
+    (r'\)\s*;\s*--(.*)\n', 'line_comment', '#pop:2'),
+    (r'\n\s*\)\s*;\s*--(.*)\n', 'port_list_comment', '#pop:2'),
+    (r'\n\s*', None),
     (r'\)\s*;', 'end_port', '#pop:2'),
     (r'--#(.*)\n', 'metacomment'),
     (r'/\*', 'block_comment', 'block_comment'),
@@ -566,7 +572,8 @@ def parse_vhdl(text):
 
     elif action == 'line_comment':
       for i in last_items:
-        i.param_desc = groups[0]
+        if not i.param_desc:
+          i.param_desc = groups[0]
 
   return objects
 
@@ -774,8 +781,9 @@ def register_array_types_from_sources(self, source_files):
   component acomp is
     port (
       a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- default value '1'
-    );
+      f,g,h : inout bit := '1' -- bit ports 
+    ); -- port list comment
+    
   end component;
 
 end package;

From 0224b76f34530c2a6153b175e94304fa8f975fe4 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 16:00:04 +0100
Subject: [PATCH 12/24] Make it Python3 friendly

---
 hdlparse/minilexer.py   | 4 ++--
 hdlparse/vhdl_parser.py | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hdlparse/minilexer.py b/hdlparse/minilexer.py
index 30121ae..bb6d14b 100644
--- a/hdlparse/minilexer.py
+++ b/hdlparse/minilexer.py
@@ -22,7 +22,7 @@ def __init__(self, tokens, flags=re.MULTILINE):
     self.tokens = {}
 
     # Pre-process the state definitions
-    for state, patterns in tokens.iteritems():
+    for state, patterns in tokens.items():
       full_patterns = []
       for p in patterns:
         pat = re.compile(p[0], flags)
@@ -33,7 +33,7 @@ def __init__(self, tokens, flags=re.MULTILINE):
         if new_state and new_state.startswith('#pop'):
           try:
             new_state = -int(new_state.split(':')[1])
-          except IndexError, ValueError:
+          except (IndexError, ValueError):
             new_state = -1
 
         full_patterns.append((pat, action, new_state))
diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 0aa7751..87c733c 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -753,7 +753,7 @@ def _register_array_types(self, objects):
     subtypes = {o.name:o.base_type for o in objects if isinstance(o, VhdlSubtype)}
 
     # Find all subtypes of an array type
-    for k,v in subtypes.iteritems():
+    for k,v in subtypes.items():
       while v in subtypes: # Follow subtypes of subtypes
         v = subtypes[v]
       if v in self.array_types:

From d980827a2b54b5413b50cd4a26f97cf6cc8f29bc Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 16:19:52 +0100
Subject: [PATCH 13/24] Add comment for param_desc attribute of class
 VhdlParameter

---
 hdlparse/vhdl_parser.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 87c733c..731577d 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -174,8 +174,9 @@ class VhdlParameter(object):
     data_type (str): Type name for the parameter
     default_value (str): Default value of the parameter
     desc (str): Description from object metacomments
+    param_desc (str): Description of the parameter
   '''
-  def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None):
+  def __init__(self, name, mode=None, data_type=None, default_value=None, desc=None, param_desc = None):
     self.name = name
     self.mode = mode
     self.data_type = data_type

From 5d05ca3fd3ee5f608104349ebbde46e8e0e6d47f Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Mon, 7 Dec 2020 14:53:11 +0100
Subject: [PATCH 14/24] Support end entity with entity keyword and name

---
 hdlparse/vhdl_parser.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 731577d..b970c6e 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -87,6 +87,7 @@
     (r'generic\s*\(', None, 'generic_list'),
     (r'port\s*\(', None, 'port_list'),
     (r'end\s+\w+\s*;', 'end_entity', '#pop'),
+    (r'end\s+entity\s+\w+\s*;', 'end_entity', '#pop'),
     (r'/\*', 'block_comment', 'block_comment'),
     (r'--.*\n', None),
   ],

From 1edc3752b6f6c9517862e3f214f98350b0d59423 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Tue, 28 Jul 2020 16:59:14 +0200
Subject: [PATCH 15/24] Add VhdlParameterType class to support vector and array
 parameter types

---
 hdlparse/vhdl_parser.py | 37 +++++++++++++++++++++++++++++++------
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index b970c6e..49b47bc 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,10 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [
@@ -187,9 +189,9 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non
 
   def __str__(self):
     if self.mode is not None:
-      param = '{} : {} {}'.format(self.name, self.mode, self.data_type)
+      param = '{} : {} {}'.format(self.name, self.mode, self.data_type.name + self.data_type.arange)
     else:
-      param = '{} : {}'.format(self.name, self.data_type)
+      param = '{} : {}'.format(self.name, self.data_type.name + self.data_type.arange)
     if self.default_value is not None:
       param = '{} := {}'.format(param, self.default_value)
     if self.param_desc is not None:
@@ -197,7 +199,27 @@ def __str__(self):
     return param
       
   def __repr__(self):
-    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type)
+    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type.name + self.data_type.arange)
+
+class VhdlParameterType(object):
+  '''Parameter type definition
+
+  Args:  
+    name (str): Name of the type
+    direction(str): "to" or "downto"
+    msb (str): A digit or a name
+    lsb (str): A digit or a name
+    arange (str): Original array range string
+  '''
+  def __init__(self, name, direction = "", msb = "", lsb = "", arange = ""):
+    self.name = name
+    self.direction = direction.strip()
+    self.msb = msb.strip()
+    self.lsb = lsb.strip()
+    self.arange = arange
+
+  def __repr__(self):
+    return "VhdlParameterType('{}','{}')".format(self.name, self.arange)
 
 class VhdlPackage(VhdlObject):
   '''Package declaration
@@ -486,7 +508,7 @@ def parse_vhdl(text):
       
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, 'in', ptype)
+        p = VhdlParameter(i, 'in', VhdlParameterType(ptype))
         generics.append(p)
         last_items.append(p)
 
@@ -505,7 +527,7 @@ def parse_vhdl(text):
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype))
         ports.append(p)
         last_items.append(p)
 
@@ -519,12 +541,15 @@ def parse_vhdl(text):
       mode, ptype = groups
       array_range_start_pos = pos[1]
 
+    elif action == 'array_range_val':
+      msb, direction, lsb = groups
+
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype + arange)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, msb, lsb, arange))
         ports.append(p)
         last_items.append(p)
 

From f8b0b5064caea694f73888195dd1988f520eab77 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Mon, 7 Dec 2020 15:26:56 +0100
Subject: [PATCH 16/24] Improve pattern for array_range_val

---
 hdlparse/vhdl_parser.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 49b47bc..80c6c06 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,12 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [

From 716de832ae23cc0565fe34c4a13fb3af91299f25 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Thu, 10 Dec 2020 15:42:28 +0100
Subject: [PATCH 17/24] Rename bound vars for array parameter types. Update
 regex

---
 hdlparse/vhdl_parser.py | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 80c6c06..88610d2 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,7 +140,7 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*(\w[\w\+-\s]+\w)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
@@ -207,15 +207,15 @@ class VhdlParameterType(object):
   Args:  
     name (str): Name of the type
     direction(str): "to" or "downto"
-    msb (str): A digit or a name
-    lsb (str): A digit or a name
+    r_bound (str): A simple expression based on digits or variable names
+    l_bound (str): A simple expression based on digits or variable names
     arange (str): Original array range string
   '''
-  def __init__(self, name, direction = "", msb = "", lsb = "", arange = ""):
+  def __init__(self, name, direction = "", r_bound = "", l_bound = "", arange = ""):
     self.name = name
     self.direction = direction.strip()
-    self.msb = msb.strip()
-    self.lsb = lsb.strip()
+    self.r_bound = r_bound.strip()
+    self.l_bound = l_bound.strip()
     self.arange = arange
 
   def __repr__(self):
@@ -542,14 +542,14 @@ def parse_vhdl(text):
       array_range_start_pos = pos[1]
 
     elif action == 'array_range_val':
-      msb, direction, lsb = groups
+      r_bound, direction, l_bound = groups
 
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, msb, lsb, arange))
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, r_bound, l_bound, arange))
         ports.append(p)
         last_items.append(p)
 
@@ -807,8 +807,9 @@ def register_array_types_from_sources(self, source_files):
 
   component acomp is
     port (
-      a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- bit ports 
+      a,b,c : in std_ulogic;    -- no default value
+      f,g,h : inout bit := '1'; -- bit ports 
+      v : in std_logic_vector(lBound -1 downto 0) -- array range
     ); -- port list comment
     
   end component;

From 9b084dfc1bd24e8bdf7f026567f890572498c610 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Thu, 27 May 2021 17:44:04 +0200
Subject: [PATCH 18/24] Store array bounds

---
 hdlparse/vhdl_parser.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 88610d2..7baf062 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,12 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*(\w[\w\+-\s]+\w)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*([\w\+\-\*/\s]+)(\s+(?:down)?to)\s+([\w\+\-\*/\s]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*([\w\+\-\*/\s]+)(\s+(?:down)?to)\s+([\w\+\-\*/\s]+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [
@@ -542,7 +542,7 @@ def parse_vhdl(text):
       array_range_start_pos = pos[1]
 
     elif action == 'array_range_val':
-      r_bound, direction, l_bound = groups
+      l_bound, direction, r_bound = groups
 
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]

From 3948474be827b642e8ef36fe0dcd45973a11c8b6 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 11:57:47 +0100
Subject: [PATCH 19/24] Add line comments to port definitions

---
 hdlparse/vhdl_parser.py | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index b970c6e..e6a7d37 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -783,9 +783,8 @@ def register_array_types_from_sources(self, source_files):
   component acomp is
     port (
       a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- bit ports 
-    ); -- port list comment
-    
+      f,g,h : inout bit := '1' -- default value '1'
+    );
   end component;
 
 end package;

From bd88fabefc8dedf15e985d5d0b25191b3a55d6cf Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Fri, 10 Jan 2020 15:52:14 +0100
Subject: [PATCH 20/24] Destinguish between line comments for ports of the same
 type and for the whole port list

---
 hdlparse/vhdl_parser.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index e6a7d37..b970c6e 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -783,8 +783,9 @@ def register_array_types_from_sources(self, source_files):
   component acomp is
     port (
       a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- default value '1'
-    );
+      f,g,h : inout bit := '1' -- bit ports 
+    ); -- port list comment
+    
   end component;
 
 end package;

From c7948e08ac1ebbf34b8e0d3fd17be844e803a408 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Tue, 28 Jul 2020 16:59:14 +0200
Subject: [PATCH 21/24] Add VhdlParameterType class to support vector and array
 parameter types

---
 hdlparse/vhdl_parser.py | 37 +++++++++++++++++++++++++++++++------
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index b970c6e..49b47bc 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,10 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
+    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [
@@ -187,9 +189,9 @@ def __init__(self, name, mode=None, data_type=None, default_value=None, desc=Non
 
   def __str__(self):
     if self.mode is not None:
-      param = '{} : {} {}'.format(self.name, self.mode, self.data_type)
+      param = '{} : {} {}'.format(self.name, self.mode, self.data_type.name + self.data_type.arange)
     else:
-      param = '{} : {}'.format(self.name, self.data_type)
+      param = '{} : {}'.format(self.name, self.data_type.name + self.data_type.arange)
     if self.default_value is not None:
       param = '{} := {}'.format(param, self.default_value)
     if self.param_desc is not None:
@@ -197,7 +199,27 @@ def __str__(self):
     return param
       
   def __repr__(self):
-    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type)
+    return "VhdlParameter('{}', '{}', '{}')".format(self.name, self.mode, self.data_type.name + self.data_type.arange)
+
+class VhdlParameterType(object):
+  '''Parameter type definition
+
+  Args:  
+    name (str): Name of the type
+    direction(str): "to" or "downto"
+    msb (str): A digit or a name
+    lsb (str): A digit or a name
+    arange (str): Original array range string
+  '''
+  def __init__(self, name, direction = "", msb = "", lsb = "", arange = ""):
+    self.name = name
+    self.direction = direction.strip()
+    self.msb = msb.strip()
+    self.lsb = lsb.strip()
+    self.arange = arange
+
+  def __repr__(self):
+    return "VhdlParameterType('{}','{}')".format(self.name, self.arange)
 
 class VhdlPackage(VhdlObject):
   '''Package declaration
@@ -486,7 +508,7 @@ def parse_vhdl(text):
       
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, 'in', ptype)
+        p = VhdlParameter(i, 'in', VhdlParameterType(ptype))
         generics.append(p)
         last_items.append(p)
 
@@ -505,7 +527,7 @@ def parse_vhdl(text):
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype))
         ports.append(p)
         last_items.append(p)
 
@@ -519,12 +541,15 @@ def parse_vhdl(text):
       mode, ptype = groups
       array_range_start_pos = pos[1]
 
+    elif action == 'array_range_val':
+      msb, direction, lsb = groups
+
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, ptype + arange)
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, msb, lsb, arange))
         ports.append(p)
         last_items.append(p)
 

From e9113b9dbc55538189eae2db3b5d5005d7dbeed6 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Mon, 7 Dec 2020 15:26:56 +0100
Subject: [PATCH 22/24] Improve pattern for array_range_val

---
 hdlparse/vhdl_parser.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 49b47bc..80c6c06 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,12 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'(\s*\w+\s*(?:(?:-?|\+?)\s*\w+\s*)+)(\s+downto|\s+to)\s*(\w+)', 'array_range_val'),
+    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [

From 235249d78b6ab559491a0fde3ac722f798965621 Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Thu, 10 Dec 2020 15:42:28 +0100
Subject: [PATCH 23/24] Rename bound vars for array parameter types. Update
 regex

---
 hdlparse/vhdl_parser.py | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 80c6c06..88610d2 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,7 +140,7 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*(\w[\w\+-\s]+\w)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
@@ -207,15 +207,15 @@ class VhdlParameterType(object):
   Args:  
     name (str): Name of the type
     direction(str): "to" or "downto"
-    msb (str): A digit or a name
-    lsb (str): A digit or a name
+    r_bound (str): A simple expression based on digits or variable names
+    l_bound (str): A simple expression based on digits or variable names
     arange (str): Original array range string
   '''
-  def __init__(self, name, direction = "", msb = "", lsb = "", arange = ""):
+  def __init__(self, name, direction = "", r_bound = "", l_bound = "", arange = ""):
     self.name = name
     self.direction = direction.strip()
-    self.msb = msb.strip()
-    self.lsb = lsb.strip()
+    self.r_bound = r_bound.strip()
+    self.l_bound = l_bound.strip()
     self.arange = arange
 
   def __repr__(self):
@@ -542,14 +542,14 @@ def parse_vhdl(text):
       array_range_start_pos = pos[1]
 
     elif action == 'array_range_val':
-      msb, direction, lsb = groups
+      r_bound, direction, l_bound = groups
 
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]
 
       last_items = []
       for i in param_items:
-        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, msb, lsb, arange))
+        p = VhdlParameter(i, mode, VhdlParameterType(ptype, direction, r_bound, l_bound, arange))
         ports.append(p)
         last_items.append(p)
 
@@ -807,8 +807,9 @@ def register_array_types_from_sources(self, source_files):
 
   component acomp is
     port (
-      a,b,c : in std_ulogic;   -- no default value
-      f,g,h : inout bit := '1' -- bit ports 
+      a,b,c : in std_ulogic;    -- no default value
+      f,g,h : inout bit := '1'; -- bit ports 
+      v : in std_logic_vector(lBound -1 downto 0) -- array range
     ); -- port list comment
     
   end component;

From 4e946e7cf037b0adab70a202a02822ddf58f644f Mon Sep 17 00:00:00 2001
From: Katharina Ceesay-Seitz <katharina.ceesay-seitz@cern.ch>
Date: Thu, 27 May 2021 17:44:04 +0200
Subject: [PATCH 24/24] Store array bounds

---
 hdlparse/vhdl_parser.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py
index 88610d2..7baf062 100644
--- a/hdlparse/vhdl_parser.py
+++ b/hdlparse/vhdl_parser.py
@@ -140,12 +140,12 @@
   ],
   'array_range': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*(\w[\w\+-\s]+\w)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*([\w\+\-\*/\s]+)(\s+(?:down)?to)\s+([\w\+\-\*/\s]+)', 'array_range_val'),
     (r'\)', 'array_range_end', '#pop'),
   ],
   'nested_parens': [
     (r'\(', 'open_paren', 'nested_parens'),
-    (r'\s*([\w\+-]+)(\s+downto|\s+to)\s+([\w\+-]+)', 'array_range_val'),
+    (r'\s*([\w\+\-\*/\s]+)(\s+(?:down)?to)\s+([\w\+\-\*/\s]+)', 'array_range_val'),
     (r'\)', 'close_paren', '#pop'),
   ],
   'block_comment': [
@@ -542,7 +542,7 @@ def parse_vhdl(text):
       array_range_start_pos = pos[1]
 
     elif action == 'array_range_val':
-      r_bound, direction, l_bound = groups
+      l_bound, direction, r_bound = groups
 
     elif action == 'array_range_end':
       arange = text[array_range_start_pos:pos[0]+1]