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Anastasiia Butko edited this page Jun 12, 2018 · 18 revisions

Verilator Testbench Environment (VTE)

Abstract

VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and build an efficient interface to existing C++ based simulators. It contains Scala-based interface and C++ testbench class. Scala interface interacts with Firtl Interpreter and generates a basic set of C++ testbench files. These files contain the list of the Device Under Test (DUT) input-output ports as well as their parameters. C++ testbench provides functionalities similar to the Chisel PeekPokeTester, such PeekPokeTester as poke, expect, step functions. As a backend it uses Verilator.

Motivation

Integration with existing system simulators written in C++, e.g. SST, gem5, BookSim, etc.

Improving testing environment

VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and builds an efficient interface to existing C++ based simulators: A. Scala-based Driver generates C++ Library (verilator APIs, DUT input/output bundles, testbench etc.) B. Test file contains similar to chisel PeekPoke Test instructions C. VTE generates the Makefile that automatically combines all generated files to create the executable

Authors

Albert Chen (University of Berkeley, CA), Anastasiia Butko, Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf (Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, California 94720)

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