Merge pull request #89 from VOGL-electronic/phy_sdr_extra_latency

phy: sdr: implement extra_latency

Author: enjoy-digital

litespi/clkgen.py

@@ -65,7 +65,7 @@ class LiteSPIClkGen(LiteXModule):
     en : Signal(), in
         Clock enable input, output clock will be generated if set to 1, 0 resets the core.
     """
-    def __init__(self, pads, device, cnt_width=8):
+    def __init__(self, pads, device, cnt_width=8, extra_latency=0):
         self.div        = div        = Signal(cnt_width)
         self.posedge    = posedge    = Signal()
         self.negedge    = negedge    = Signal()
@@ -80,14 +80,15 @@ def __init__(self, pads, device, cnt_width=8):
         ]
 
         # Delayed edge to account for IO register delays.
-        self.posedge_reg  = posedge_reg  = Signal()
+        posedge_reg  = Signal(1 + 1 + int(extra_latency))
         self.posedge_reg2 = posedge_reg2 = Signal()
 
         self.sync += [
-            posedge_reg.eq(posedge),
-            posedge_reg2.eq(posedge_reg),
+            posedge_reg.eq(Cat(posedge_reg[1:], posedge)),
         ]
 
+        self.comb += posedge_reg2.eq(posedge_reg[:1])
+
         self.sync += [
             If(en | en_int,
                 If(cnt < div,

litespi/phy/generic.py

@@ -41,8 +41,8 @@ class LiteSPIPHY(LiteXModule):
     rate : str
         Rate: 1:1 SDR, 1:2 DDR.
 
-    extra_latency : int (1:2 rate)
-        Compensate for additional DDROutput/Input latency
+    extra_latency : int
+        Compensate for additional Output/Input latency
 
     Attributes
     ----------
@@ -56,12 +56,12 @@ class LiteSPIPHY(LiteXModule):
         Flash CS signal from ``LiteSPIPHYCore``.
     """
 
-    def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", extra_latency=0, **kwargs):
+    def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", **kwargs):
         assert rate in ["1:1", "1:2"]
         if rate == "1:1":
-            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay)
+            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay, **kwargs)
         if rate == "1:2":
-            phy = LiteSPIDDRPHYCore(pads, flash, cs_delay, extra_latency)
+            phy = LiteSPIDDRPHYCore(pads, flash, cs_delay, **kwargs)
 
         self.flash = flash
 

litespi/phy/generic_ddr.py

@@ -52,7 +52,7 @@ class LiteSPIDDRPHYCore(LiteXModule):
     cs : Signal(), in
         Flash CS signal.
     """
-    def __init__(self, pads, flash, cs_delay, extra_latency=0):
+    def __init__(self, pads, flash, cs_delay, extra_latency=0, **kwargs):
         self.source = source = stream.Endpoint(spi_phy2core_layout)
         self.sink   = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs              = Signal().like(pads.cs_n)

litespi/phy/generic_sdr.py

@@ -59,7 +59,7 @@ class LiteSPISDRPHYCore(LiteXModule):
     clk_divisor : CSRStorage
         Register which holds a clock divisor value applied to clkgen.
     """
-    def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay):
+    def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay, extra_latency=0, **kwargs):
         self.source           = source = stream.Endpoint(spi_phy2core_layout)
         self.sink             = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs               = Signal().like(pads.cs_n)
@@ -87,7 +87,7 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             assert not flash.ddr
 
         # Clock Generator.
-        self.clkgen = clkgen = LiteSPIClkGen(pads, device)
+        self.clkgen = clkgen = LiteSPIClkGen(pads, device, extra_latency=extra_latency)
 
         # CS control.
         self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, cs_delay)
@@ -119,7 +119,8 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
                 )
 
         # Data Shift Registers.
-        sr_cnt       = Signal(8, reset_less=True)
+        sr_out_cnt   = Signal(len(sink.len), reset_less=True)
+        sr_in_cnt    = Signal(len(sink.len), reset_less=True)
         sr_out_load  = Signal()
         sr_out_shift = Signal()
         sr_out       = Signal().like(sink.data)
@@ -159,7 +160,8 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             # Wait for CS and a CMD from the Core.
             If(cs_control.enable & sink.valid,
                 # Load Shift Register Count/Data Out.
-                NextValue(sr_cnt, sink.len - sink.width),
+                NextValue(sr_out_cnt, sink.len - sink.width),
+                NextValue(sr_in_cnt, sink.len),
                 NextValue(dq_oe, sink.mask),
                 sr_out_load.eq(1),
                 # Start XFER.
@@ -177,25 +179,34 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             If(clkgen.negedge, sr_out_shift.eq(1)),
 
             # Shift Register Count Update/Check.
+            If(clkgen.posedge_reg2,
+                NextValue(sr_in_cnt, sr_in_cnt - sink.width),
+            ),
             If(self.clkgen.negedge,
-                NextValue(sr_cnt, sr_cnt - sink.width),
+                NextValue(sr_out_cnt, sr_out_cnt - sink.width),
                 # End XFer.
-                If(sr_cnt == 0,
+                If(sr_out_cnt == 0,
                     NextState("XFER-END"),
                 ),
             ),
 
         )
         fsm.act("XFER-END",
-            # Last data already captured in XFER when divisor > 0 so only capture for divisor == 0.
-            If((spi_clk_divisor > 0) | clkgen.posedge_reg2,
-                # Accept CMD.
+            If(sr_in_cnt == 0,
                 sink.ready.eq(1),
-                # Capture last data (only for spi_clk_divisor == 0).
-                sr_in_shift.eq(spi_clk_divisor == 0),
                 # Send Status/Data to Core.
                 NextState("SEND-STATUS-DATA"),
-            )
+            ).Else(
+                sr_in_shift.eq(clkgen.posedge_reg2),
+                If(clkgen.posedge_reg2,
+                    NextValue(sr_in_cnt, sr_in_cnt - sink.width),
+                    If(sr_in_cnt == sink.width,
+                       sink.ready.eq(1),
+                       # Send Status/Data to Core.
+                       NextState("SEND-STATUS-DATA"),
+                    ),
+                ),
+            ),
         )
         self.comb += source.data.eq(sr_in)
         fsm.act("SEND-STATUS-DATA",