Merge pull request #85 from VOGL-electronic/add_irq

master: add irq

Author: enjoy-digital

litespi/__init__.py

@@ -14,7 +14,7 @@
 from litespi.crossbar import LiteSPICrossbar
 from litespi.core.master import LiteSPIMaster
 from litespi.core.mmap import LiteSPIMMAP
-
+from litespi.phy.generic import LiteSPIPHY
 
 class LiteSPICore(Module):
     def __init__(self):
@@ -24,6 +24,7 @@ def __init__(self):
 
 
 class LiteSPI(LiteXModule):
+    autocsr_exclude = {"ev"}
     """SPI Controller wrapper.
 
     The ``LiteSPI`` class provides a wrapper that can instantiate both ``LiteSPIMMAP`` and ``LiteSPIMaster`` and connect them to the PHY.
@@ -70,8 +71,8 @@ class LiteSPI(LiteXModule):
 
     def __init__(self, phy, clock_domain="sys",
         with_mmap=True, mmap_endianness="big",
-        with_master=True, master_tx_fifo_depth=1, master_rx_fifo_depth=1,
-        with_csr=True, with_mmap_write=False, mmap_cs_mask=1):
+        with_master=True, master_tx_fifo_depth=1, master_rx_fifo_depth=1, master_with_irq=False,
+        with_csr=True, with_mmap_write=False, mmap_cs_mask=1, **kwargs):
 
         cs_width=len(phy.cs)
 
@@ -97,12 +98,15 @@ def __init__(self, phy, clock_domain="sys",
             self.master = master = LiteSPIMaster(
                 tx_fifo_depth = master_tx_fifo_depth,
                 rx_fifo_depth = master_rx_fifo_depth,
+                with_irq = master_with_irq,
                 cs_width = cs_width)
             port_master = crossbar.get_port(master.cs)
             self.comb += [
                 port_master.source.connect(master.sink),
                 master.source.connect(port_master.sink),
             ]
+            if hasattr(master, "ev"):
+                self.ev = master.ev
 
         if clock_domain != "sys":
             self.comb += [
@@ -114,3 +118,18 @@ def __init__(self, phy, clock_domain="sys",
                 crossbar.master.source.connect(phy.sink),
                 phy.source.connect(crossbar.master.sink),
             ]
+
+class LiteSPIWrapper(LiteXModule):
+    autocsr_exclude = {"ev"}
+    def __init__(self, pads=None, module=None, phy=None, **kwargs):
+        assert pads is not None or module is not None, "Either pads or module must be provided."
+        # PHY.
+        self.phy = LiteSPIPHY(pads, module, **kwargs) if phy is None else phy
+
+        # Core.
+        self.core = LiteSPI(self.phy, **kwargs)
+
+        if hasattr(self.core, "bus"):
+            self.bus = self.core.bus
+        if hasattr(self.core, "ev"):
+            self.ev = self.core.ev

litespi/core/master.py

@@ -10,6 +10,7 @@
 
 from litex.soc.interconnect import stream
 from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.csr_eventmanager import *
 
 from litespi.common import *
 
@@ -41,7 +42,7 @@ class LiteSPIMaster(LiteXModule):
         Slave CS signal.
 
     """
-    def __init__(self, cs_width=1, tx_fifo_depth=1, rx_fifo_depth=1):
+    def __init__(self, cs_width=1, tx_fifo_depth=1, rx_fifo_depth=1, with_irq=False):
         self.sink   = stream.Endpoint(spi_phy2core_layout)
         self.source = stream.Endpoint(spi_core2phy_layout)
         self.cs     = Signal(cs_width)
@@ -86,3 +87,12 @@ def __init__(self, cs_width=1, tx_fifo_depth=1, rx_fifo_depth=1):
             self._status.fields.rx_ready.eq(rx_fifo.source.valid),
             self._rxtx.w.eq(rx_fifo.source.data),
         ]
+
+        if with_irq:
+            self.ev            = EventManager()
+            self.ev.rx_ready   = EventSourceProcess(edge="rising")
+            self.ev.finalize()
+
+            self.comb += [
+                self.ev.rx_ready.trigger.eq(rx_fifo.source.valid),
+            ]

litespi/phy/generic.py

@@ -56,7 +56,7 @@ class LiteSPIPHY(LiteXModule):
         Flash CS signal from ``LiteSPIPHYCore``.
     """
 
-    def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", extra_latency=0):
+    def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", extra_latency=0, **kwargs):
         assert rate in ["1:1", "1:2"]
         if rate == "1:1":
             phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay)