phy: add **kwargs

add **kwargs

Signed-off-by: Fin Maaß <[email protected]>

Author: maass-hamburg

litespi/phy/generic.py

@@ -60,9 +60,9 @@ class LiteSPIPHY(LiteXModule):
     def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", **kwargs):
         assert rate in ["1:1", "1:2"]
         if rate == "1:1":
-            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay)
+            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay, **kwargs)
         if rate == "1:2":
-            phy = LiteSPIDDRPHYCore2(pads, flash, clock_domain, default_divisor, cs_delay)
+            phy = LiteSPIDDRPHYCore2(pads, flash, clock_domain, default_divisor, cs_delay, **kwargs)
 
         self.flash = flash
 

litespi/phy/generic_ddr_with_clk.py

@@ -56,7 +56,7 @@ class LiteSPIDDRPHYCore2(LiteXModule):
     clk_divisor : CSRStorage
         Register which holds a clock divisor value applied to clkgen.
     """
-    def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay, extra_latency=0):
+    def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay, extra_latency=0, **kwargs):
         self.source           = source = stream.Endpoint(spi_phy2core_layout)
         self.sink             = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs               = Signal().like(pads.cs_n)

litespi/phy/generic_sdr.py

@@ -59,7 +59,7 @@ class LiteSPISDRPHYCore(LiteXModule):
     clk_divisor : CSRStorage
         Register which holds a clock divisor value applied to clkgen.
     """
-    def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay):
+    def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay, **kwargs):
         self.source           = source = stream.Endpoint(spi_phy2core_layout)
         self.sink             = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs               = Signal().like(pads.cs_n)