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phy: add ddr variant with clk divider #86

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phy: add ddr variant with clk divider #86

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@maass-hamburg maass-hamburg commented Aug 7, 2025 •
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  • add ddr variant with clk divider
  • change sdr variant to use a compatible clk divider with the ddr variant
  • add clk drivider csr per core module
  • extra_latency: adds support for sdr phy, for ddr phy more granular (0,5 steps)
  • cs timer: moves delay to start, when cs is not active, so in a lot of cases when using it, we don't have to wait anymore

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@enjoy-digital should it replace the old ddr phy without a clk divider or should it stay as in alternative?

maass-hamburg added a commit to VOGL-electronic/gw__litex that referenced this pull request Aug 22, 2025
@maass-hamburg
litespi: use new clk divisor
8bdf1e9 
use new clk divisor, that is used
for SDR and DDR from
litex-hub/litespi#86

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg maass-hamburg force-pushed the ddr_clk_variable branch 3 times, most recently from ccfa073 to 65a1e4e Compare August 22, 2025 12:56
@maass-hamburg maass-hamburg mentioned this pull request Aug 22, 2025
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@maass-hamburg maass-hamburg marked this pull request as ready for review August 22, 2025 12:59
@maass-hamburg maass-hamburg mentioned this pull request Aug 22, 2025
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maass-hamburg added a commit to VOGL-electronic/gw__litex that referenced this pull request Aug 26, 2025
@maass-hamburg
litespi: use new clk divisor
f804999 
use new clk divisor, that is used
for SDR and DDR from
litex-hub/litespi#86

Signed-off-by: Fin Maaß <[email protected]>
maass-hamburg added a commit to VOGL-electronic/gw__litex that referenced this pull request Sep 3, 2025
@maass-hamburg
litespi: use new clk divisor
fb4505a 
use new clk divisor, that is used
for SDR and DDR from
litex-hub/litespi#86

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
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@enjoy-digital please take a look. I already tested this successfully with efinix titanium and Topaz.

maass-hamburg added a commit to VOGL-electronic/gw__litex that referenced this pull request Sep 4, 2025
@maass-hamburg
litespi: use new clk divisor
7f1ee12 
use new clk divisor, that is used
for SDR and DDR from
litex-hub/litespi#86

Signed-off-by: Fin Maaß <[email protected]>
maass-hamburg added a commit to VOGL-electronic/gw__litex that referenced this pull request Sep 8, 2025
@maass-hamburg
litespi: use new clk divisor
e96b249 
use new clk divisor, that is used
for SDR and DDR from
litex-hub/litespi#86

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg maass-hamburg mentioned this pull request Sep 16, 2025
Merged
@maass-hamburg
phy: improve DDR phy
bc299c1 
improve existing DDR.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
phy: add DDR phy with clock divider
644d2d2 
This commit adds a DDR PHY implementation with a clock divider to the LiteSPI project.
The clock divider enables the use of a lower frequency clock while still achieving the desired data rate.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
phy: sdr: use a clk divider compatible with ddr
2da7654 
use a clk divider compatible with the ddr one.
This way the software doen't have to know
which phy is used. for sdr only every 2 values
the effective clk divider changes, it is rounded up
so we don't so we are never faster than the matching
freq.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
core: be able to set clk dividers independent per core
7ba9aef 
be able to set clk dividers independent per core.
When using the master sometimes we need a
slower speed, in order to not change it for mmap
and make that slower too, they now can be set per
core module. When the clk divider is not set in the
core module (by it being 0), the phy will use the
 clk divider it's own csr.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
WIP: use ddr with clk divider
e2ba7ad 
use ddr with clk divider

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
phy: start cs timer already when cs is falling
d3bc37a 
start cs timer already when cs is falling,
instead of when it's going to be used.

Signed-off-by: Fin Maaß <[email protected]>
@maass-hamburg
phy: use comb logic for clk div, when provided by core
bb3746f 
use comb logic for clk div, when provided by core,
so it can directly be used, when it's avalible.
NEeded due to the change of start of the cs timer.

Signed-off-by: Fin Maaß <[email protected]>
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@maass-hamburg