diff --git a/src/mame/sinclair/tsconf.cpp b/src/mame/sinclair/tsconf.cpp
index f7861e7e4d5df..964dffa0ea1fe 100644
--- a/src/mame/sinclair/tsconf.cpp
+++ b/src/mame/sinclair/tsconf.cpp
@@ -28,7 +28,6 @@ FAQ-RUS: https://forum.tslabs.info/viewtopic.php?f=35&t=157
     ROM: https://github.com/tslabs/zx-evo/blob/master/pentevo/rom/bin/ts-bios.rom (validated on: 2021-12-14)
 
 TODO:
-- Ram cache
 - VDos
 
  ****************************************************************************/
@@ -71,13 +70,13 @@ TILE_GET_INFO_MEMBER(tsconf_state::get_tile_info_16c)
 
 void tsconf_state::tsconf_mem(address_map &map)
 {
-	map(0x0000, 0x3fff).bankr(m_bank_ram[0]).w(FUNC(tsconf_state::tsconf_bank_w<0>));
+	map(0x0000, 0x3fff).rw(FUNC(tsconf_state::tsconf_ram_bank_r<0>), FUNC(tsconf_state::tsconf_bank_w<0>));
 	map(0x0000, 0x3fff).view(m_bank0_rom);
 	m_bank0_rom[0](0x0000, 0x3fff).bankr(m_bank_rom[0]);
 
-	map(0x4000, 0x7fff).bankr(m_bank_ram[1]).w(FUNC(tsconf_state::tsconf_bank_w<1>));
-	map(0x8000, 0xbfff).bankr(m_bank_ram[2]).w(FUNC(tsconf_state::tsconf_bank_w<2>));
-	map(0xc000, 0xffff).bankr(m_bank_ram[3]).w(FUNC(tsconf_state::tsconf_bank_w<3>));
+	map(0x4000, 0x7fff).rw(FUNC(tsconf_state::tsconf_ram_bank_r<1>), FUNC(tsconf_state::tsconf_bank_w<1>));
+	map(0x8000, 0xbfff).rw(FUNC(tsconf_state::tsconf_ram_bank_r<2>), FUNC(tsconf_state::tsconf_bank_w<2>));
+	map(0xc000, 0xffff).rw(FUNC(tsconf_state::tsconf_ram_bank_r<3>), FUNC(tsconf_state::tsconf_bank_w<3>));
 }
 
 void tsconf_state::tsconf_io(address_map &map)
@@ -119,12 +118,6 @@ void tsconf_state::tsconf_switch(address_map &map)
 	map(0x4000, 0xffff).r(FUNC(tsconf_state::beta_disable_r));
 }
 
-template <u8 Bank>
-void tsconf_state::tsconf_bank_w(offs_t offset, u8 data)
-{
-	tsconf_state::ram_bank_write(Bank, offset, data);
-}
-
 static const gfx_layout spectrum_charlayout =
 {
 	8, 8,          // 8 x 8 characters
@@ -186,7 +179,8 @@ void tsconf_state::machine_start()
 	m_bank_ram[0]->configure_entries(0, m_ram->size() / 0x4000, m_ram->pointer(), 0x4000);
 
 	save_item(NAME(m_int_mask));
-	save_pointer(NAME(m_regs), 0x100);
+	save_item(NAME(m_regs));
+	save_item(NAME(m_cache_line_addr));
 	save_item(NAME(m_zctl_di));
 	save_item(NAME(m_zctl_cs));
 	save_item(NAME(m_port_f7_ext));
@@ -201,6 +195,7 @@ void tsconf_state::machine_reset()
 	m_int_mask = 0;
 
 	m_bank0_rom.select(0);
+	m_cache_line_addr = -1;
 
 	m_glukrs->disable();
 
diff --git a/src/mame/sinclair/tsconf.h b/src/mame/sinclair/tsconf.h
index 2c579387b51af..5f113850e323b 100644
--- a/src/mame/sinclair/tsconf.h
+++ b/src/mame/sinclair/tsconf.h
@@ -200,9 +200,9 @@ class tsconf_state : public spectrum_128_state
 	void tsconf_mem(address_map &map) ATTR_COLD;
 	void tsconf_switch(address_map &map) ATTR_COLD;
 
-	u8 mem_bank_read(u8 bank, offs_t offset);
-	template <u8 Bank>
-	void tsconf_bank_w(offs_t offset, u8 data);
+	template <u8 Bank> u8 tsconf_ram_bank_r(offs_t offset) { return ram_bank_read(Bank, offset); };
+	template <u8 Bank> void tsconf_bank_w(offs_t offset, u8 data) { ram_bank_write(Bank, offset, data); };
+	u8 ram_bank_read(u8 bank, offs_t offset);
 	void ram_bank_write(u8 bank, offs_t offset, u8 data);
 	void ram_page_write(u8 page, offs_t offset, u8 data);
 	void cram_write(u16 offset, u8 data);
@@ -219,6 +219,7 @@ class tsconf_state : public spectrum_128_state
 	memory_view m_bank0_rom;
 	memory_share_array_creator<u8, 2> m_tiles_raw;
 	memory_share_creator<u8> m_sprites_raw;
+	u16 m_cache_line_addr; // u13
 
 	required_device<at_keyboard_device> m_keyboard;
 	required_ioport_array<3> m_io_mouse;
diff --git a/src/mame/sinclair/tsconf_m.cpp b/src/mame/sinclair/tsconf_m.cpp
index bf1f05ecad979..b8222251189ce 100644
--- a/src/mame/sinclair/tsconf_m.cpp
+++ b/src/mame/sinclair/tsconf_m.cpp
@@ -359,8 +359,27 @@ void tsconf_state::draw_sprites(screen_device &screen_d, bitmap_rgb32 &bitmap, c
 
 }
 
+u8 tsconf_state::ram_bank_read(u8 bank, offs_t offset)
+{
+	if (!machine().side_effects_disabled() && ((m_regs[SYS_CONFIG] & 3) == 2)) // 14Mhz
+	{
+		const u16 cpu_hi_addr = ((m_regs[PAGE0 + bank]) << 5) | BIT(offset, 9, 5);
+		if (!(m_regs[CACHE_CONFIG] & (1 << bank)) || (cpu_hi_addr != m_cache_line_addr))
+		{
+			m_cache_line_addr = cpu_hi_addr;
+			m_maincpu->adjust_icount(-2);
+		}
+	}
+
+	return reinterpret_cast<u8 *>(m_bank_ram[bank]->base())[offset];
+}
+
 void tsconf_state::ram_bank_write(u8 bank, offs_t offset, u8 data)
 {
+	const u16 cpu_hi_addr = ((m_regs[PAGE0 + bank]) << 5) | BIT(offset, 9, 5);
+	if (cpu_hi_addr == m_cache_line_addr)
+		m_cache_line_addr = -1; // invalidate cache line
+
 	if (BIT(m_regs[FMAPS], 4))
 	{
 		offs_t machine_addr = PAGE4K(bank) + offset;
@@ -703,9 +722,9 @@ void tsconf_state::tsconf_port_xxaf_w(offs_t port, u8 data)
 	case FMAPS:
 	case TS_CONFIG:
 	case INT_MASK:
+	case CACHE_CONFIG:
 	// TODO
 	case FDD_VIRT:
-	case CACHE_CONFIG:
 		break;
 
 	default: