@@ -312,14 +312,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = {
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{ IMX214_REG_DIG_CROP_WIDTH , 4096 },
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{ IMX214_REG_DIG_CROP_HEIGHT , 2304 },
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- { IMX214_REG_VTPXCK_DIV , IMX214_DEFAULT_VTPXCK_DIV },
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- { IMX214_REG_VTSYCK_DIV , IMX214_DEFAULT_VTSYCK_DIV },
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- { IMX214_REG_PREPLLCK_VT_DIV , IMX214_DEFAULT_PREPLLCK_VT_DIV },
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- { IMX214_REG_PLL_VT_MPY , IMX214_DEFAULT_PLL_VT_MPY },
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- { IMX214_REG_OPPXCK_DIV , IMX214_DEFAULT_OPPXCK_DIV },
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- { IMX214_REG_OPSYCK_DIV , IMX214_DEFAULT_OPSYCK_DIV },
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- { IMX214_REG_PLL_MULT_DRIV , IMX214_PLL_SINGLE },
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-
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{ IMX214_REG_REQ_LINK_BIT_RATE ,
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IMX214_LINK_BIT_RATE_MBPS (IMX214_LINK_BIT_RATE (IMX214_DEFAULT_CLK_FREQ )) },
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@@ -376,14 +368,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = {
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{ IMX214_REG_DIG_CROP_WIDTH , 1920 },
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{ IMX214_REG_DIG_CROP_HEIGHT , 1080 },
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- { IMX214_REG_VTPXCK_DIV , IMX214_DEFAULT_VTPXCK_DIV },
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- { IMX214_REG_VTSYCK_DIV , IMX214_DEFAULT_VTSYCK_DIV },
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- { IMX214_REG_PREPLLCK_VT_DIV , IMX214_DEFAULT_PREPLLCK_VT_DIV },
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- { IMX214_REG_PLL_VT_MPY , IMX214_DEFAULT_PLL_VT_MPY },
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- { IMX214_REG_OPPXCK_DIV , IMX214_DEFAULT_OPPXCK_DIV },
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- { IMX214_REG_OPSYCK_DIV , IMX214_DEFAULT_OPSYCK_DIV },
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- { IMX214_REG_PLL_MULT_DRIV , IMX214_PLL_SINGLE },
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-
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{ IMX214_REG_REQ_LINK_BIT_RATE ,
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IMX214_LINK_BIT_RATE_MBPS (IMX214_LINK_BIT_RATE (IMX214_DEFAULT_CLK_FREQ )) },
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@@ -420,9 +404,6 @@ static const struct cci_reg_sequence mode_table_common[] = {
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/* ATR setting */
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{ IMX214_REG_ATR_FAST_MOVE , 2 },
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- /* external clock setting */
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- { IMX214_REG_EXCK_FREQ , IMX214_EXCK_FREQ (IMX214_DEFAULT_CLK_FREQ / 1000000 ) },
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-
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/* global setting */
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/* basic config */
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{ IMX214_REG_MASK_CORR_FRAMES , IMX214_CORR_FRAMES_MASK },
@@ -792,6 +773,30 @@ static int imx214_entity_init_state(struct v4l2_subdev *subdev,
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return 0 ;
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}
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+ static int imx214_set_clock (struct imx214 * imx214 )
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+ {
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+ int ret = 0 ;
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+
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+ cci_write (imx214 -> regmap , IMX214_REG_VTPXCK_DIV ,
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+ IMX214_DEFAULT_VTPXCK_DIV , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_VTSYCK_DIV ,
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+ IMX214_DEFAULT_VTSYCK_DIV , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_PREPLLCK_VT_DIV ,
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+ IMX214_DEFAULT_PREPLLCK_VT_DIV , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_PLL_VT_MPY ,
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+ IMX214_DEFAULT_PLL_VT_MPY , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_OPPXCK_DIV ,
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+ IMX214_DEFAULT_OPPXCK_DIV , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_OPSYCK_DIV ,
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+ IMX214_DEFAULT_OPSYCK_DIV , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_PLL_MULT_DRIV ,
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+ IMX214_PLL_SINGLE , & ret );
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+ cci_write (imx214 -> regmap , IMX214_REG_EXCK_FREQ ,
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+ IMX214_EXCK_FREQ (IMX214_DEFAULT_CLK_FREQ / 1000000 ), & ret );
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+
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+ return ret ;
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+ }
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+
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static int imx214_update_digital_gain (struct imx214 * imx214 , u32 val )
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{
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int ret = 0 ;
@@ -1033,6 +1038,12 @@ static int imx214_start_streaming(struct imx214 *imx214)
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return ret ;
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}
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+ ret = imx214_set_clock (imx214 );
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+ if (ret ) {
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+ dev_err (imx214 -> dev , "failed to configure clock %d\n" , ret );
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+ return ret ;
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+ }
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+
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ret = cci_write (imx214 -> regmap , IMX214_REG_CSI_LANE_MODE ,
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IMX214_CSI_4_LANE_MODE , NULL );
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if (ret ) {
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