Writing to a fixed address with descriptor-based approach

[Jorgebrihu]

Hello,

I want to use cheshire and add to it an iDMA. More concretely, I want to use the descriptor-based approach as I want to be able to read from incremented memory addresses and write to a fixed memory address (as far as I understood, only the descriptor-based iDMA allows me to do that).

I have used the following pull request: https://github.com/pulp-platform/cheshire/pull/183 , that already implements both register and descriptor-based. I have made a transaction, just modifying bits 4:1 of the element flags of the descriptor to 0x1(burst type for source -> incr: 01 and burst type for dst -> fixed: 00). I understand this is all I need in order to write to a fixed address, isn't it?

I have tested that with the following src and dst data:

uint64_t src[8] = {0x1111, 0x2222, 0x3333, 0x4444, 0x5555, 0x6666, 0x7777, 0x8888};
uint64_t dst[8] = {0, 0, 0, 0, 0, 0, 0, 0};

And I get the following output:

Value of dst[00000000]: 0000000000001111
Value of dst[00000001]: 0000000000000000
Value of dst[00000002]: 0000000000000000
Value of dst[00000003]: 0000000000000000
Value of dst[00000004]: 0000000000002222
Value of dst[00000005]: 0000000000000000
Value of dst[00000006]: 0000000000000000
Value of dst[00000007]: 0000000000000000
Value of dst[00000008]: 0000000000003333
Value of dst[00000009]: 0000000000000000
Value of dst[0000000A]: 0000000000000000
Value of dst[0000000B]: 0000000000000000
Value of dst[0000000C]: 0000000000004444
...

However, I expected that all components of the vector would be written and overwrite dst[0], expecting then the following:

Value of dst[00000000]: 0000000000008888
Value of dst[00000001]: 0000000000000000
Value of dst[00000002]: 0000000000000000
...

I have added an ILA to the signal in axi_write_req_o port in idma_backend_rw_axi.sv and the value of the aw.addr increments, which I do not understand as the transfer is set to be wrtiting to a fixed memory address.

I have gone through the code and as the documentation says, the legalizer is in charge of the "Burst splitting". However, the part legalizing the write transaction in idma_legalizer_rw_axi.sv does not seem to take into account the burst configuration of the transaction:

//--------------------------------------
// Legalize write transaction
//--------------------------------------
// more bytes remaining than we can write

        if (w_tf_q.length > w_num_bytes_possible) begin
            w_num_bytes = w_num_bytes_possible;
            // calculate remainder
            w_tf_d.length = w_tf_q.length - w_num_bytes_possible;
            // next address
            w_tf_d.addr = w_tf_q.addr + w_num_bytes;

        // remaining bytes fit in one burst
        end else begin
            w_num_bytes = w_tf_q.length[PageAddrWidth:0];
            // finished
            w_tf_d.valid = 1'b0;
            w_done = 1'b1;
        end

Does this make sense?

What am I doing wrong so it is not working? Am I missing something while configuring the descriptor for the transaction or what I want to do is not yet implemented?

Any hint is appreciated.
Thanks in advanced

[thommythomaso]

We currently only support incremental bursts in the legalizer. When first designing the unit, we thought about implementing fixed bursts as well, but ran into some involved edge cases when dealing with narrow sub-bus transfers. Fixed bursts for bus-aligned transfers could relatively easily be implemented.