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Some Bundles are flattened in the viewer: hierarchy is not preserved when the hardware type of a signal is specified for the single fields #20

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@rameloni

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@rameloni

When the hardware type of the fields of a bundle is specified in the fields instead of the root, the waveform is not able to render the hierarchy of that bundle. In the code below it's the case of MyMixedBundle where the actual hardware signals are myMixedBundle.a and myMixedBundle.b. myMixedBundle is only a scala variable and it is not a hardware variable like myIOBundle, therefore it is not passed to firtool and the information cannot be available in the viewer.

class MyBundle extends Bundle {
  val x = UInt(32.W)
  val y = UInt(32.W)
}

class MyIOBundle extends Bundle {
  val w = Input(UInt(32.W))
  val z = Output(UInt(32.W))
}

class MyMixedBundle extends Bundle {
  val a = WireInit(0.U(32.W))
  val b = IO(Output(UInt(32.W)))
}

class Foo extends Module {
  val myBundleValIO   = IO(Input(new MyBundle))
  val myBundleValWire = Wire(new MyBundle)
  val myBundleValReg  = Reg(new MyBundle)

  val myIOBundle = IO(new MyIOBundle)

  val myMixedBundle = new MyMixedBundle

  // Connections
  myBundleValWire := myBundleValIO
  myBundleValReg  := myBundleValIO

  myIOBundle.z := 18.U

  myMixedBundle.a := myBundleValIO.x
  myMixedBundle.b := myMixedBundle.a
}

issue-hierarchy-not-visible-for-some-bundles

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    bugSomething isn't workinginternals-chiselThe issue is related to the internals of chisel

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