The uart printf statements block or do not print

[stdefeber]

Describe the bug
I have written an srecord loader for the NEORV32.
Please see code attached.
When compiling this code as application, it seems to work, except for being able to write to IMEM, since IMEM becomes a ROM when the
int_bootloader_en flag is false.

When compiling it as bootloader, so with int_bootloader_en flag is true, it does not pass the initial printf statement.
Replacing the neorv32_uart0_printf with a macro, as defined in the bootloader example code, the srecord parser works.
This is what is currently implemented in the attached code.

To Reproduce

• replace PRINT_TEXT with neorv32_uart0_printf
• compile attached code with bootloader as target

Expected behavior
The srecord loader should at least print "<>"

Screenshots
If applicable, add screenshots to help explain your problem.

Environment:

• Ubuntu 24.04.1 LTS
• GCC Version
  • RISC-V: 13.2.0
  • native: 13.3.0
• Libraries used: mpfr, libmpc

Hardware:

• Hardware version 1.10.5
• Implemented CPU extensions: C, M,
• peripherals, 2*uart, i2c, spi, gpio, mtime, xbus, imem, dmem, debugger
• Hardware modifications: None

bootloader.txt

[Unike267]

Your design works fine!

I've simulated it for 15 ms and obtained the following result:

At first, I got an incorrect outcome because you had set BAUD_RATE to 115200 instead of 19200.

To reproduce the simulation, follow these steps:

• Install podman:
  • sudo apt install podman
• Download the required images:
  • podman pull ghcr.io/stnolting/neorv32/sim:latest (To compile software)
  • podman pull docker.io/ghdl/vunit:mcode-master (To perform simulation)
• Set up the simulation environment:
  • mkdir tmp
  • cd tmp
  • git clone --recursive https://github.com/stnolting/neorv32-setups
  • cd neorv32-setups
  • mkdir sim
  • cd sim

Create the following four files inside the sim directory (with these exact names):

run.py

#!/usr/bin/env python3

from pathlib import Path
from vunit import VUnit
from shutil import copyfile
from os import makedirs, getenv
import re

vu = VUnit.from_argv()
vu.add_vhdl_builtins()

ROOT = Path(__file__).parent

NEORV32 = vu.add_library("neorv32")
NEORV32.add_source_files([
    ROOT / "*.vhd",
    ROOT / "../neorv32/rtl/core/*.vhd", 
])

vu.main()

tb_top.vhd

library ieee;
context ieee.ieee_std_context;

library neorv32;
use neorv32.neorv32_package.all;

library vunit_lib;
context vunit_lib.vunit_context;

entity tb_top is
  generic (
    runner_cfg : string
  );
end entity;

architecture tb of tb_top is

signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic := '0';
signal gpio_a : std_ulogic_vector(7 downto 0);
signal uart0_txd : std_logic;

constant baud0_rate_c            : natural := 19200;
constant CLOCK_FREQUENCY         : natural := 100000000;

constant uart0_baud_val_c : real := real(CLOCK_FREQUENCY) / real(baud0_rate_c);

constant clk_period : time := 10 ns;

  -- Logging

  constant logger : logger_t := get_logger("tb_top");
  constant file_handler : log_handler_t := new_log_handler(
    output_path(runner_cfg) & "log.csv",
    format => csv,
    use_color => false
  );

signal start, done: boolean := false;

begin

neorv32_test_0 : entity work.neorv32_test
                                             generic map(
                                                         CLOCK_FREQUENCY => CLOCK_FREQUENCY,
                                                         MEM_INT_IMEM_SIZE => 22528,
                                                         MEM_INT_DMEM_SIZE => 8192
                                                        )
                                             port map   (
                                                         clk_i => clk,
                                                         rstn_i => rstn,
                                                         gpio_o => gpio_a,
                                                         uart0_txd_o => uart0_txd,
                                                         uart0_rxd_i => uart0_txd
                                                        );
  -- UART Simulation Receiver ---------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  uart0_checker: entity work.uart_rx_simple
  generic map (
    name => "uart0",
    uart_baud_val_c => uart0_baud_val_c
  )
  port map (
    clk => clk,
    uart_txd => uart0_txd
  );

clk <= not clk after clk_period/2;
rstn <= not rst;

  main: process
  begin
    test_runner_setup(runner, runner_cfg);
    while test_suite loop
      if run("test") then
        set_log_handlers(logger, (display_handler, file_handler));
        show_all(logger, file_handler);
        show_all(logger, display_handler);

        rst <= '1';
        wait for 15*clk_period;
        rst <= '0';
        info(logger, "Init test");
        wait until rising_edge(clk);
        start <= true;
        wait until rising_edge(clk);
        start <= false;
        wait until (done and rising_edge(clk));
        info(logger, "Test done");
      end if;
    end loop;
    test_runner_cleanup(runner);
    wait;
  end process;

  test: process
  begin
    done <= false;
    wait until start and rising_edge(clk);
    
    
    wait for 15 ms;
    done <= true;
    wait;
  end process;

end architecture;

neorv32_test.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library neorv32;

entity neorv32_test is
  generic (
    -- adapt these for your setup --
    CLOCK_FREQUENCY   : natural := 100000000; -- clock frequency of clk_i in Hz
    MEM_INT_IMEM_SIZE : natural := 26*1024;   -- size of processor-internal instruction memory in bytes
    MEM_INT_DMEM_SIZE : natural := 8*1024     -- size of processor-internal data memory in bytes
  );
  port (
    -- Global control --
    clk_i       : in  std_ulogic; -- global clock, rising edge
    rstn_i      : in  std_ulogic; -- global reset, low-active, async
    -- GPIO --
    gpio_o      : out std_ulogic_vector(7 downto 0); -- parallel output
    -- UART0 --
    uart0_txd_o : out std_ulogic; -- UART0 send data
    uart0_rxd_i : in  std_ulogic  -- UART0 receive data
  );
end entity;

architecture neorv32_rtl of neorv32_test is

  -- internal IO connection --
  signal con_gpio_o : std_ulogic_vector(31 downto 0);

begin

  -- The Core Of The Problem ----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  neorv32_top_inst:  entity work.neorv32_top
  generic map (
    -- General --
    CLOCK_FREQUENCY              => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz
    BOOT_MODE_SELECT             => 2,                 -- boot configuration select (Implement IMEM as pre-initialized ROM)
    -- RISC-V CPU Extensions --
    RISCV_ISA_C                  => true,              -- implement compressed extension?
    RISCV_ISA_M                  => true,              -- implement mul/div extension?
    RISCV_ISA_Zicntr             => true,              -- implement base counters?
    -- Internal Instruction memory --
    MEM_INT_IMEM_EN              => true,              -- implement processor-internal instruction memory
    MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
    -- Internal Data memory --
    MEM_INT_DMEM_EN              => true,              -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
    -- Processor peripherals --
    IO_GPIO_NUM                  => 8,                 -- number of GPIO input/output pairs (0..64)
    IO_CLINT_EN                  => true,              -- implement machine system timer (MTIME)?
    IO_UART0_EN                  => true               -- implement primary universal asynchronous receiver/transmitter (UART0)?
  )
  port map (
    -- Global control --
    clk_i       => clk_i,       -- global clock, rising edge
    rstn_i      => rstn_i,      -- global reset, low-active, async
    -- GPIO (available if IO_GPIO_EN = true) --
    gpio_o      => con_gpio_o,  -- parallel output
    -- primary UART0 (available if IO_GPIO_NUM > 0) --
    uart0_txd_o => uart0_txd_o, -- UART0 send data
    uart0_rxd_i => uart0_rxd_i  -- UART0 receive data
  );

    -- GPIO output --
    gpio_o <= con_gpio_o(7 downto 0);
end architecture;

uart_rx.simple.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

use std.textio.all;

entity uart_rx_simple is
  generic (
    name : string;
    uart_baud_val_c : real);

  port (
    clk : in std_ulogic;
    uart_txd : in std_ulogic
    );
end entity;

architecture a of uart_rx_simple is
  signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
  signal uart_rx_busy : std_ulogic := '0';
  signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
  signal uart_rx_baud_cnt : real;
  signal uart_rx_bitcnt : natural;

  file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & name & ".out";

begin
  uart_rx_console : process(clk)
    variable i : integer;
    variable l : line;
  begin
    -- "UART" --
    if rising_edge(clk) then
      -- synchronizer --
      uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
      -- arbiter --
      if (uart_rx_busy = '0') then  -- idle
        uart_rx_busy <= '0';
        uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
        uart_rx_bitcnt <= 9;
        if (uart_rx_sync(4 downto 1) = "1100") then  -- start bit? (falling edge)
          uart_rx_busy <= '1';
        end if;
      else
        if (uart_rx_baud_cnt <= 0.0) then
          if (uart_rx_bitcnt = 1) then
            uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c);
          else
            uart_rx_baud_cnt <= round(uart_baud_val_c);
          end if;
          if (uart_rx_bitcnt = 0) then
            uart_rx_busy <= '0';  -- done
            i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));

            if (i < 32) or (i > 32+95) then  -- printable char?
              report name & ".tx: (" & integer'image(i) & ")";  -- print code
            else
              report name & ".tx: " & character'val(i);  -- print ASCII
            end if;

            if (i = 10) then  -- Linux line break
              writeline(file_uart_tx_out, l);
            elsif (i /= 13) then  -- Remove additional carriage return
              write(l, character'val(i));
            end if;
          else
            uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
            uart_rx_bitcnt <= uart_rx_bitcnt - 1;
          end if;
        else
          uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
        end if;
      end if;
    end if;
  end process uart_rx_console;
end architecture;

• (Continue with the setup:)
  • chmod +x run.py
  • cd ..
  • cd neorv32/sw/example
  • mkdir test
  • cp hello_world/makefile test/makefile
  • cd test
  • Paste your software file bootloader.c, making sure to modify the baud rate.
  • cd ../../..
  • Compile the software:
    • podman run --rm -itv $(pwd):/wrk:Z -w /wrk stnolting/neorv32/sim:latest sh -c "RISCV_PREFIX=riscv32-unknown-elf- make -C sw/example/test clean_all MARCH=rv32imac_zicsr_zifencei info image" ⚠️SEE EDIT⚠️
  • cp sw/example/test/neorv32_application_image.vhd rtl/core/neorv32_application_image.vhd
  • cd ..
  • Run the simulation:
    • podman run --rm -itv $(pwd):/wrk:Z -w /wrk ghdl/vunit:mcode-master ./sim/run.py -v --gtkwave-fmt vcd

Cheers! 🎉

---

EDIT:

Since stnolting/neorv32-setups#222, specifying the RISCV_PREFIX is no longer necessary for the compilation. To do that, simply apply:

• podman run --rm -itv $(pwd):/wrk:Z -w /wrk stnolting/neorv32/sim:latest sh -c "make -C sw/example/test clean_all MARCH=rv32imac_zicsr_zifencei info image"

[stdefeber]

Thanks for reproducing.

Have you replaced the PRINT_TEXT with neorv32_uart0_printf ?

[Unike267]

Thanks for reproducing.

You're welcome.

Have you replaced the PRINT_TEXT with neorv32_uart0_printf ?

No, I haven't.

I've used your code without modifying anything except the baud rate.

The word "Bootloader" printed in the simulation comes from the following line:

268: PRINT_TEXT("\n \n <<Bootloader >> \n\n");

[stdefeber]

The issue arises when using the neorv32_uart0_printf

[Unike267]

Oh, sorry!

I tend to read issues diagonally and assumed the attached program was the one to be tested.

If you attach the program you want me to test, I'll do it.

If you don’t mind a suggestion, adding a picture of the error would also help. For example, if you simulated your design using the tips I gave you yesterday, you could show the result you got.

Cheers! 😃

[Unike267]

Hi @stdefeber!

I've relaunched the simulation, replacing all PRINT_TEXT functions with neorv32_uart0_printf, and it seems to be working fine.

As we can see in the following image:

Are you still experiencing issues with this?

Cheers!

[Unike267]

This is the C software and the application_image.vhd that I used.

bootloader.txt

neorv32_application_image.txt

[stnolting]

@stdefeber

Hardware version 1.10.5

Could upgrade to the most recent version of the core? I think it is then easier (for us) to track the error if necessary.

@Unike267

Thank you very much for your support!

[stdefeber]

Will do.

I will come back to it in a couple of days.

[Unike267]

Hi @stdefeber!

Any progress on this? 🤔