diff --git a/src/board/system76/bonw16/board.c b/src/board/system76/bonw16/board.c new file mode 100644 index 000000000..2cb8a23c9 --- /dev/null +++ b/src/board/system76/bonw16/board.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-3.0-only + +#include +#include +#include +#include +#include + +void board_init(void) { + espi_init(); + + // Make sure charger is in off state, also enables PSYS + battery_charger_disable(); + + // Allow backlight to be turned on + gpio_set(&BKL_EN, true); + // Enable camera + gpio_set(&CCD_EN, true); +} + +void board_event(void) { + espi_event(); + + ec_read_post_codes(); +} diff --git a/src/board/system76/bonw16/board.mk b/src/board/system76/bonw16/board.mk new file mode 100644 index 000000000..6734f7ba4 --- /dev/null +++ b/src/board/system76/bonw16/board.mk @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-3.0-only + +board-y += board.c +board-y += gpio.c + +EC = ite +CONFIG_EC_ITE_IT5570E = y +CONFIG_EC_FLASH_SIZE_256K = y + +# Intel-based host +CONFIG_PLATFORM_INTEL = y +CONFIG_BUS_ESPI = y + +# Enable firmware security +CONFIG_SECURITY = y + +# Include keyboard +KEYBOARD = 15in_102 + +# Set keyboard LED mechanism +CONFIG_HAVE_KBLED = y +KBLED = bonw14 + +# Set battery I2C bus +CFLAGS += -DI2C_SMBUS=I2C_4 + +# Set touchpad PS2 bus +CFLAGS += -DPS2_TOUCHPAD=PS2_3 + +# Set smart charger parameters +# XXX: PRS1 and PRS2 are in parallel for adapter Rsense? +CHARGER = oz26786 +CFLAGS += \ + -DCHARGER_ADAPTER_RSENSE=5 \ + -DCHARGER_BATTERY_RSENSE=5 \ + -DCHARGER_CHARGE_CURRENT=3072 \ + -DCHARGER_CHARGE_VOLTAGE=17100 \ + -DCHARGER_INPUT_CURRENT=16500 + +# Set USB-PD parameters +CONFIG_HAVE_USBPD = y +CONFIG_USBPD_TPS65987 = y +CFLAGS += -DI2C_USBPD=I2C_1 + +# Set CPU power limits in watts +CFLAGS += \ + -DPOWER_LIMIT_AC=330 \ + -DPOWER_LIMIT_DC=55 + +# Enable dGPU support +CONFIG_HAVE_DGPU = y +CFLAGS += -DI2C_DGPU=I2C_1 + +# Fan configs +CFLAGS += -DFAN1_PWM=DCR2 +CFLAGS += -DBOARD_FAN1_POINTS="\ + FAN_POINT(60, 40), \ + FAN_POINT(65, 60), \ + FAN_POINT(70, 75), \ + FAN_POINT(75, 90), \ + FAN_POINT(80, 100), \ +" + +CFLAGS += -DFAN2_PWM=DCR4 +CFLAGS += -DBOARD_FAN2_POINTS="\ + FAN_POINT(60, 40), \ + FAN_POINT(65, 60), \ + FAN_POINT(70, 75), \ + FAN_POINT(75, 90), \ + FAN_POINT(80, 100), \ +" + +# Add system76 common code +include src/board/system76/common/common.mk diff --git a/src/board/system76/bonw16/gpio.c b/src/board/system76/bonw16/gpio.c new file mode 100644 index 000000000..3e729edbf --- /dev/null +++ b/src/board/system76/bonw16/gpio.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-3.0-only + +#include +#include + +// uncrustify:off +struct Gpio __code ACIN_N = GPIO(B, 0); +struct Gpio __code AC_PRESENT = GPIO(E, 1); +struct Gpio __code ALL_SYS_PWRGD = GPIO(C, 0); +struct Gpio __code BKL_EN = GPIO(C, 7); +struct Gpio __code BUF_PLT_RST_N = GPIO(D, 2); // renamed to ESPI_RESET_N +struct Gpio __code CCD_EN = GPIO(D, 1); +struct Gpio __code DD_ON = GPIO(E, 4); +struct Gpio __code DGPU_PWR_EN = GPIO(J, 2); +struct Gpio __code EC_EN = GPIO(B, 6); // renamed to SUSBC_EC# +struct Gpio __code EC_RSMRST_N = GPIO(E, 5); +struct Gpio __code GC6_FB_EN = GPIO(J, 3); +struct Gpio __code JACK_IN_N = GPIO(E, 6); +struct Gpio __code LAN_WAKEUP_N = GPIO(B, 2); +struct Gpio __code LED_ACIN = GPIO(H, 2); +struct Gpio __code LED_BAT_CHG = GPIO(H, 5); +struct Gpio __code LED_BAT_FULL = GPIO(J, 0); +struct Gpio __code LED_PWR = GPIO(D, 0); +struct Gpio __code LID_SW_N = GPIO(B, 1); +struct Gpio __code ME_WE = GPIO(I, 2); +struct Gpio __code PCH_DPWROK_EC = GPIO(F, 3); +struct Gpio __code PCH_PWROK_EC = GPIO(C, 6); // renamed to PM_PWROK_EC +struct Gpio __code PWR_BTN_N = GPIO(D, 5); +struct Gpio __code PWR_SW_N = GPIO(B, 3); +struct Gpio __code SINK_CTRL = GPIO(H, 0); +struct Gpio __code SLP_SUS_N = GPIO(H, 7); +struct Gpio __code VA_EC_EN = GPIO(J, 4); +struct Gpio __code WLAN_PWR_EN = GPIO(B, 5); +struct Gpio __code XLP_OUT = GPIO(B, 4); +// uncrustify:on + +static const struct GpioInit __code gpio_cfg_init[] = { + // General control + //TODO!! + { &GCR9, BIT(5) }, // PWRSW WDT 2 Enable 2 + { &GCR8, BIT(4) }, // PWRSW WDT 2 Enable 1 + { &GCR, 0x04 }, // Enable LPC reset on GPD2 + { &GCR6, 0 }, // Disable UARTs + { &GCR15, BIT(4) }, // Enable SMBus channel 4 + { &GCR19, BIT(0) }, // Set GPD2 to 1.8V + { &GCR20, 0 }, // Set GPF2 and GPF3 to 3.3V + { &GCR1, 0 }, + { &GCR2, 0 }, + { &GCR10, 0x02 }, + { &GCR21, 0 }, + { &GCR22, 0x80 }, + { &GCR23, BIT(0) }, // Set GPM6 power domain to VCC + + // Port data + { &GPDRA, 0 }, + { &GPDRB, BIT(4) | BIT(3) }, // XLP_OUT, PWR_SW# + { &GPDRC, 0 }, + { &GPDRD, BIT(3) }, // BL_PWM_EN_EC + { &GPDRE, BIT(3) }, // USB_PWR_EN# (inverted) + { &GPDRF, BIT(3) }, // PCH_DPWROK_EC + { &GPDRG, BIT(6) | BIT(0) }, // H_PROCHOT#_EC, PLVDD_RST_EC + { &GPDRH, BIT(6) }, // EC_AMP_EN + { &GPDRI, 0 }, + { &GPDRJ, BIT(1) }, // KBC_MUTE# + + // Port control + { &GPCRA0, GPIO_IN }, // EC_PWM_PIN_24 + { &GPCRA1, GPIO_IN }, // LG_DET# + { &GPCRA2, GPIO_ALT }, // CPU_FAN + { &GPCRA3, GPIO_ALT }, // DDS_EC_PWM + { &GPCRA4, GPIO_ALT }, // VGA_FAN + { &GPCRA5, GPIO_ALT }, // EC_PWM_LED_R + { &GPCRA6, GPIO_ALT }, // EC_PWM_LED_G + { &GPCRA7, GPIO_ALT }, // EC_PWM_LED_B + + { &GPCRB0, GPIO_IN | GPIO_UP }, // AC_IN# + { &GPCRB1, GPIO_IN | GPIO_UP }, // LID_SW# + { &GPCRB2, GPIO_IN | GPIO_UP }, // EC_LAN_WAKEUP# + { &GPCRB3, GPIO_IN }, // PWR_SW# + { &GPCRB4, GPIO_OUT }, // XLP_OUT + { &GPCRB5, GPIO_OUT }, // WLAN_PWR_EN + { &GPCRB6, GPIO_OUT | GPIO_UP }, // SUSBC_EC# + + { &GPCRC0, GPIO_IN }, // ALL_SYS_PWRGD + { &GPCRC1, GPIO_ALT | GPIO_UP }, // SMC_VGA_THERM + { &GPCRC2, GPIO_ALT | GPIO_UP }, // SMD_VGA_THERM + { &GPCRC3, GPIO_ALT | GPIO_UP }, // KB-SO16 + { &GPCRC4, GPIO_IN | GPIO_UP }, // CNVI_DET# + { &GPCRC5, GPIO_ALT | GPIO_UP }, // KB-SO17 + { &GPCRC6, GPIO_OUT }, // PM_PWROK_EC + { &GPCRC7, GPIO_OUT | GPIO_UP }, // BKL_EN + + { &GPCRD0, GPIO_OUT }, // LED_PWR + { &GPCRD1, GPIO_OUT | GPIO_UP }, // CCD_EN + { &GPCRD2, GPIO_ALT }, // ESPI_RESET_N + { &GPCRD3, GPIO_OUT }, // BL_PWM_EN_EC + { &GPCRD4, GPIO_OUT }, // MUX_CTRL_BIOS + { &GPCRD5, GPIO_OUT | GPIO_UP }, // PWR_BTN# + { &GPCRD6, GPIO_ALT | GPIO_DOWN }, // CPU_FANSEN + { &GPCRD7, GPIO_ALT | GPIO_DOWN }, // VGA_FANSEN + + { &GPCRE0, GPIO_ALT | GPIO_UP }, // SMC_BAT + { &GPCRE1, GPIO_OUT | GPIO_UP }, // AC_PRESENT + { &GPCRE2, GPIO_IN }, // N/C + { &GPCRE3, GPIO_OUT }, // USB_PWR_EN# + { &GPCRE4, GPIO_OUT | GPIO_DOWN }, // DD_ON + { &GPCRE5, GPIO_OUT }, // EC_RSMRST# + { &GPCRE6, GPIO_IN }, // JACK_IN#_EC + { &GPCRE7, GPIO_ALT | GPIO_UP }, // SMD_BAT + + { &GPCRF0, GPIO_OUT | GPIO_UP }, // 80CLK + { &GPCRF1, GPIO_OUT | GPIO_UP }, // USB_CHARGE_EN + { &GPCRF2, GPIO_OUT | GPIO_UP }, // 3IN1 + { &GPCRF3, GPIO_OUT }, // PCH_DPWROK_EC + { &GPCRF4, GPIO_ALT | GPIO_UP }, // TP_CLK + { &GPCRF5, GPIO_ALT | GPIO_UP }, // TP_DATA + { &GPCRF6, GPIO_ALT }, // SLP_S0_N + { &GPCRF7, GPIO_IN }, // CPU_C10_GATE_N + + { &GPCRG0, GPIO_OUT }, // PLVDD_RST_EC + { &GPCRG1, GPIO_OUT }, // PD_VIN_3V3_EC + { &GPCRG2, GPIO_IN }, // 100k pull-up + { &GPCRG3, GPIO_ALT }, // ALSPI_CE#_L + { &GPCRG4, GPIO_ALT }, // ALSPI_MSI_L + { &GPCRG5, GPIO_ALT }, // ALSPI_MSO_L + { &GPCRG6, GPIO_OUT | GPIO_UP }, // H_PROCHOT#_EC + { &GPCRG7, GPIO_ALT }, // ALSPI_SCLK_L + + { &GPCRH0, GPIO_IN }, // SINK_CTRL + { &GPCRH1, GPIO_OUT }, // PD_PWR_EC_EN# + { &GPCRH2, GPIO_OUT | GPIO_UP }, // LED_ACIN + { &GPCRH3, GPIO_IN }, // PD_I2C_IRQ# + { &GPCRH4, GPIO_IN }, // dGPU_OVERT_EC + { &GPCRH5, GPIO_OUT | GPIO_UP }, // LED_BAT_CHG + { &GPCRH6, GPIO_OUT }, // EC_AMP_EN + { &GPCRH7, GPIO_IN }, // SLP_SUS# + + { &GPCRI0, GPIO_ALT }, // BAT_DET + { &GPCRI1, GPIO_ALT }, // BAT_VOLT + { &GPCRI2, GPIO_IN | GPIO_DOWN }, // ME_WE + { &GPCRI3, GPIO_ALT }, // THERM_VOLT_CPU + { &GPCRI4, GPIO_ALT }, // TOTAL_CUR + { &GPCRI5, GPIO_ALT }, // THERM_VOLT_DDR + { &GPCRI6, GPIO_ALT }, // THERM_VOLT_GPU + { &GPCRI7, GPIO_ALT }, // BOARD_ID_ADC + + { &GPCRJ0, GPIO_OUT | GPIO_UP }, // LED_BAT_FULL + { &GPCRJ1, GPIO_OUT }, // KBC_MUTE# + { &GPCRJ2, GPIO_IN }, // DGPU_PWR_EN + { &GPCRJ3, GPIO_IN }, // GPIO1_GC6_FB_EN_3V3 + { &GPCRJ4, GPIO_OUT }, // VA_EC_EN + { &GPCRJ5, GPIO_IN }, // VBATT_BOOST# + { &GPCRJ6, GPIO_OUT | GPIO_UP }, // EC_GPIO + { &GPCRJ7, GPIO_IN | GPIO_UP }, // PERKB_DET# + + { &GPCRM0, GPIO_ALT | GPIO_UP | GPIO_DOWN }, // ESPI_IO0_EC + { &GPCRM1, GPIO_ALT | GPIO_UP | GPIO_DOWN }, // ESPI_IO1_EC + { &GPCRM2, GPIO_ALT | GPIO_UP | GPIO_DOWN }, // ESPI_IO2_EC + { &GPCRM3, GPIO_ALT | GPIO_UP | GPIO_DOWN }, // ESPI_IO3_EC + { &GPCRM4, GPIO_ALT | GPIO_UP | GPIO_DOWN }, // ESPI_CLK_EC + { &GPCRM5, GPIO_ALT }, // ESPI_CS_EC# + { &GPCRM6, GPIO_IN | GPIO_UP | GPIO_DOWN }, // ESPI_ALERT0# +}; + +void gpio_init(void) { + for (uint8_t i = 0; i < ARRAY_SIZE(gpio_cfg_init); i++) { + *gpio_cfg_init[i].reg = gpio_cfg_init[i].data; + } +} diff --git a/src/board/system76/bonw16/include/board/gpio.h b/src/board/system76/bonw16/include/board/gpio.h new file mode 100644 index 000000000..b9d9c9c05 --- /dev/null +++ b/src/board/system76/bonw16/include/board/gpio.h @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-3.0-only + +#ifndef _BOARD_GPIO_H +#define _BOARD_GPIO_H + +#include + +void gpio_init(void); + +extern struct Gpio __code ACIN_N; +extern struct Gpio __code AC_PRESENT; +extern struct Gpio __code ALL_SYS_PWRGD; +extern struct Gpio __code BKL_EN; +#define HAVE_BT_EN 0 +extern struct Gpio __code BUF_PLT_RST_N; +extern struct Gpio __code CCD_EN; +extern struct Gpio __code CPU_C10_GATE_N; +extern struct Gpio __code DD_ON; +extern struct Gpio __code DGPU_PWR_EN; +extern struct Gpio __code EC_EN; +extern struct Gpio __code EC_RSMRST_N; +extern struct Gpio __code GC6_FB_EN; +extern struct Gpio __code JACK_IN_N; +extern struct Gpio __code LAN_WAKEUP_N; +extern struct Gpio __code LED_ACIN; +#define HAVE_LED_AIRPLANE_N 0 +extern struct Gpio __code LED_BAT_CHG; +extern struct Gpio __code LED_BAT_FULL; +extern struct Gpio __code LED_PWR; +extern struct Gpio __code LID_SW_N; +extern struct Gpio __code ME_WE; +extern struct Gpio __code PCH_DPWROK_EC; +extern struct Gpio __code PCH_PWROK_EC; +#define HAVE_PM_PWROK 0 +extern struct Gpio __code PWR_BTN_N; +extern struct Gpio __code PWR_SW_N; +extern struct Gpio __code SINK_CTRL; +extern struct Gpio __code SLP_SUS_N; +#define HAVE_SUS_PWR_ACK 0 +extern struct Gpio __code VA_EC_EN; +#define HAVE_WLAN_EN 0 +extern struct Gpio __code WLAN_PWR_EN; +extern struct Gpio __code XLP_OUT; + +#endif // _BOARD_GPIO_H