[Yosys+Odin-II]: fix cpp format

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

ODIN_II/SRC/BLIFReader.cpp

@@ -1191,7 +1191,7 @@ operation_list BLIF::Reader::read_bit_map_find_unknown_gate(int input_count, nno
             /* Assumption that bit map is in order when read from blif */
             else if (line_count_bitmap == 2) {
                 /* LOGICAL_XOR */
-                if (((strcmp(bit_map[0], "01") == 0) && (strcmp(bit_map[1], "10") == 0)) || ((strcmp(bit_map[0], "10") == 0) && (strcmp(bit_map[1], "01") == 0)))  {
+                if (((strcmp(bit_map[0], "01") == 0) && (strcmp(bit_map[1], "10") == 0)) || ((strcmp(bit_map[0], "10") == 0) && (strcmp(bit_map[1], "01") == 0))) {
                     to_return = LOGICAL_XOR;
                 }
                 /* LOGICAL_XNOR */
@@ -1380,7 +1380,7 @@ void BLIF::Reader::create_latch_node_and_driver() {
         // to avoid concatenating the top module name to edge sentivity and init value inputs
         if (configuration.coarsen && (input_token_count == 3 || input_token_count == 5))
             names[input_token_count - 1] = resolve_signal_name_based_on_blif_type(nullptr, ptr);
-        else            
+        else
             names[input_token_count - 1] = resolve_signal_name_based_on_blif_type(blif_netlist->identifier, ptr);
     }
 

ODIN_II/SRC/BLIFWriter.cpp

@@ -343,7 +343,7 @@ void BLIF::Writer::output_blif(FILE* out, const netlist_t* netlist) {
             warn_undriven(node, net);
             for (int j = 0; j < net->num_driver_pins; j++) {
                 // skip if their names is identical
-                if(coarsen_cleanup && net->driver_pins[j]->name && node->name && !strcmp(net->driver_pins[j]->name, node->name))
+                if (coarsen_cleanup && net->driver_pins[j]->name && node->name && !strcmp(net->driver_pins[j]->name, node->name))
                     continue;
                 fprintf(out, ".names");
                 print_net_driver(out, node, net, j);

ODIN_II/SRC/YYosys.cpp

@@ -274,7 +274,7 @@ void YYosys::execute() {
         switch (configuration.input_file_type) {
             case (file_type_e::_VERILOG): // fallthrough
             case (file_type_e::_VERILOG_HEADER): {
-                    run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
+                run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
                 break;
             }
             case (file_type_e::_SYSTEM_VERILOG): {
@@ -293,12 +293,7 @@ void YYosys::execute() {
 #    else
         run_pass(std::string("read_verilog -sv -nolatches " + aggregated_circuits));
 #    endif
-        /* 
-         * Check whether cells match libraries, find top module, and run the Yosys basic coarse-grained synthesis steps
-         * such as proc: Translate processes to netlist components such as MUXs, FFs and latches
-         * or fsm: Extraction and optimization of finite state machines
-         * the option "-noalumacc" is to avoid Yosys transforms basic arithmetic operations into alu or macc
-        */
+        // Check whether cells match libraries and find top module
         if (global_args.top_level_module_name.provenance() == argparse::Provenance::SPECIFIED) {
             run_pass(std::string("hierarchy -check -top " + global_args.top_level_module_name.value() + " -purge_lib"));
         } else {
@@ -328,7 +323,6 @@ void YYosys::execute() {
          */
         run_pass(std::string("share; opt;"));
 
-
         // Use a readable name convention
         // [NOTE]: the 'autoname' process has a high memory footprint for giant netlists
         // we run it after basic optimization passes to reduce the overhead (see issue #2031)
@@ -353,7 +347,7 @@ void YYosys::execute() {
          *         initial implementation of Yosys+Odin-II, which did not use this pass
          */
         run_pass(std::string("techmap */t:$mem */t:$memrd */t:$add */t:$sub */t:$mul */t:$dffsr */t:$dffsre */t:$sr */t:$dlatch */t:$adlatch %% %n"));
-        
+
         // Collects memories, their port and create multiport memory cells
         run_pass(std::string("memory_collect; memory_dff;"));
         /**
@@ -374,7 +368,6 @@ void YYosys::execute() {
         // Turn all DFFs into simple latches
         run_pass(std::string("dffunmap; opt -fast -noff;"));
 
-
         // Check the hierarchy for any unknown modules, and purge all modules (including blackboxes) that aren't used
         run_pass(std::string("hierarchy -check -purge_lib"));
         // "-undriven" to ensure there is no wire without drive

ODIN_II/SRC/netlist_utils.cpp

@@ -1903,7 +1903,7 @@ void equalize_input_ports_size(nnode_t*& node, uintptr_t traverse_mark_number, n
     /* no change is needed */
     if (port_a_size == port_y_size)
         return;
-    
+
     /**
      * INPUTS
      *  A: (width_a)