|
5048 | 5048 | <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/>
|
5049 | 5049 | </layer>
|
5050 | 5050 | </fixed_layout>
|
| 5051 | + <fixed_layout name="neuron3d" width="92" height="68"> |
| 5052 | + <layer die="1"> |
| 5053 | + <!-- Stratix IV IO blocks connect to both horizontal and vertical |
| 5054 | + routing channels. We approximate this by placing them one unit |
| 5055 | + 'in' from the true perimeter (which is left empty). This means |
| 5056 | + that they are fully surrounded by routing channels, allowing them |
| 5057 | + to connect to both horizontal and vertical channels. This is a |
| 5058 | + minor approximation since on real Stratix IV devices there is no |
| 5059 | + perimeter-side vertical routing channel --> |
| 5060 | + <perimeter type="EMPTY" priority="5000"/> |
| 5061 | + <col type="io" startx="1" priority="1001"/> |
| 5062 | + <!-- Left side --> |
| 5063 | + <col type="io" startx="W-2" priority="1001"/> |
| 5064 | + <!-- Right side --> |
| 5065 | + <row type="io" starty="1" priority="1000"/> |
| 5066 | + <!-- Bottom side --> |
| 5067 | + <row type="io" starty="H-2" priority="1000"/> |
| 5068 | + <!-- Top side --> |
| 5069 | + <!-- Stratix IV devices support up to 16 Global clocks and 12 PLLs located |
| 5070 | + around the device perimeter as indicated in Figure 5-1 of Chapter 5 |
| 5071 | + of the Stratix IV handbook. |
| 5072 | + |
| 5073 | + Note the use of different priorities to avoid ambiguity on small devices --> |
| 5074 | + <single type="PLL" x="1" y="H-2" priority="1997"/> |
| 5075 | + <!-- L1 --> |
| 5076 | + <single type="PLL" x="1" y="H/2" priority="2000"/> |
| 5077 | + <!-- L2 --> |
| 5078 | + <single type="PLL" x="1" y="H/2 - 1" priority="1999"/> |
| 5079 | + <!-- L3 --> |
| 5080 | + <single type="PLL" x="1" y="1" priority="1998"/> |
| 5081 | + <!-- L4 --> |
| 5082 | + <single type="PLL" x="W - 2" y="H-2" priority="1997"/> |
| 5083 | + <!-- R1 --> |
| 5084 | + <single type="PLL" x="W - 2" y="H/2" priority="2000"/> |
| 5085 | + <!-- R2 --> |
| 5086 | + <single type="PLL" x="W - 2" y="H/2 - 1" priority="1999"/> |
| 5087 | + <!-- R3 --> |
| 5088 | + <single type="PLL" x="W - 2" y="1" priority="1998"/> |
| 5089 | + <!-- R4 --> |
| 5090 | + <single type="PLL" x="W/2" y="H-2" priority="1996"/> |
| 5091 | + <!-- T1 --> |
| 5092 | + <single type="PLL" x="W/2 + 1" y="H-2" priority="1995"/> |
| 5093 | + <!-- T2 --> |
| 5094 | + <single type="PLL" x="W/2 - 1" y="H-2" priority="1992"/> |
| 5095 | + <!-- GCLK --> |
| 5096 | + <single type="PLL" x="W/2 + 2" y="H-2" priority="1991"/> |
| 5097 | + <!-- GCLK --> |
| 5098 | + <single type="PLL" x="W/2" y="1" priority="1994"/> |
| 5099 | + <!-- B1 --> |
| 5100 | + <single type="PLL" x="W/2 + 1" y="1" priority="1993"/> |
| 5101 | + <!-- B2 --> |
| 5102 | + <single type="PLL" x="W/2 - 1" y="1" priority="1990"/> |
| 5103 | + <!-- GCLK --> |
| 5104 | + <single type="PLL" x="W/2 + 2" y="1" priority="1989"/> |
| 5105 | + <!-- GCLK --> |
| 5106 | + <!--Fill with 'LAB'--> |
| 5107 | + <fill type="LAB" priority="10"/> |
| 5108 | + <!--Column of 'DSP' with 'EMPTY' blocks wherever a 'DSP' does not fit. Vertical offset by 1 for perimeter.--> |
| 5109 | + <col type="DSP" startx="6" starty="2" repeatx="40" priority="150"/> |
| 5110 | + <col type="EMPTY" startx="6" repeatx="40" starty="1" priority="149"/> |
| 5111 | + <!--Column of 'M9K' with 'EMPTY' blocks wherever a 'M9K' does not fit. Vertical offset by 1 for perimeter.--> |
| 5112 | + <col type="M9K" startx="5" starty="2" repeatx="26" priority="50"/> |
| 5113 | + <col type="EMPTY" startx="5" repeatx="26" starty="1" priority="49"/> |
| 5114 | + <!--Column of 'M144K' with 'EMPTY' blocks wherever a 'M144K' does not fit. Vertical offset by 1 for perimeter.--> |
| 5115 | + <col type="M144K" startx="33" starty="2" repeatx="43" priority="100"/> |
| 5116 | + <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/> |
| 5117 | + </layer> |
| 5118 | + <layer die="0"> |
| 5119 | + <!-- Stratix IV IO blocks connect to both horizontal and vertical |
| 5120 | + routing channels. We approximate this by placing them one unit |
| 5121 | + 'in' from the true perimeter (which is left empty). This means |
| 5122 | + that they are fully surrounded by routing channels, allowing them |
| 5123 | + to connect to both horizontal and vertical channels. This is a |
| 5124 | + minor approximation since on real Stratix IV devices there is no |
| 5125 | + perimeter-side vertical routing channel --> |
| 5126 | + <perimeter type="EMPTY" priority="5000"/> |
| 5127 | + <col type="io" startx="1" priority="1001"/> |
| 5128 | + <!-- Left side --> |
| 5129 | + <col type="io" startx="W-2" priority="1001"/> |
| 5130 | + <!-- Right side --> |
| 5131 | + <row type="io" starty="1" priority="1000"/> |
| 5132 | + <!-- Bottom side --> |
| 5133 | + <row type="io" starty="H-2" priority="1000"/> |
| 5134 | + <!-- Top side --> |
| 5135 | + <!-- Stratix IV devices support up to 16 Global clocks and 12 PLLs located |
| 5136 | + around the device perimeter as indicated in Figure 5-1 of Chapter 5 |
| 5137 | + of the Stratix IV handbook. |
| 5138 | + |
| 5139 | + Note the use of different priorities to avoid ambiguity on small devices --> |
| 5140 | + <single type="PLL" x="1" y="H-2" priority="1997"/> |
| 5141 | + <!-- L1 --> |
| 5142 | + <single type="PLL" x="1" y="H/2" priority="2000"/> |
| 5143 | + <!-- L2 --> |
| 5144 | + <single type="PLL" x="1" y="H/2 - 1" priority="1999"/> |
| 5145 | + <!-- L3 --> |
| 5146 | + <single type="PLL" x="1" y="1" priority="1998"/> |
| 5147 | + <!-- L4 --> |
| 5148 | + <single type="PLL" x="W - 2" y="H-2" priority="1997"/> |
| 5149 | + <!-- R1 --> |
| 5150 | + <single type="PLL" x="W - 2" y="H/2" priority="2000"/> |
| 5151 | + <!-- R2 --> |
| 5152 | + <single type="PLL" x="W - 2" y="H/2 - 1" priority="1999"/> |
| 5153 | + <!-- R3 --> |
| 5154 | + <single type="PLL" x="W - 2" y="1" priority="1998"/> |
| 5155 | + <!-- R4 --> |
| 5156 | + <single type="PLL" x="W/2" y="H-2" priority="1996"/> |
| 5157 | + <!-- T1 --> |
| 5158 | + <single type="PLL" x="W/2 + 1" y="H-2" priority="1995"/> |
| 5159 | + <!-- T2 --> |
| 5160 | + <single type="PLL" x="W/2 - 1" y="H-2" priority="1992"/> |
| 5161 | + <!-- GCLK --> |
| 5162 | + <single type="PLL" x="W/2 + 2" y="H-2" priority="1991"/> |
| 5163 | + <!-- GCLK --> |
| 5164 | + <single type="PLL" x="W/2" y="1" priority="1994"/> |
| 5165 | + <!-- B1 --> |
| 5166 | + <single type="PLL" x="W/2 + 1" y="1" priority="1993"/> |
| 5167 | + <!-- B2 --> |
| 5168 | + <single type="PLL" x="W/2 - 1" y="1" priority="1990"/> |
| 5169 | + <!-- GCLK --> |
| 5170 | + <single type="PLL" x="W/2 + 2" y="1" priority="1989"/> |
| 5171 | + <!-- GCLK --> |
| 5172 | + <!--Fill with 'LAB'--> |
| 5173 | + <fill type="LAB" priority="10"/> |
| 5174 | + <!--Column of 'DSP' with 'EMPTY' blocks wherever a 'DSP' does not fit. Vertical offset by 1 for perimeter.--> |
| 5175 | + <col type="DSP" startx="6" starty="2" repeatx="40" priority="150"/> |
| 5176 | + <col type="EMPTY" startx="6" repeatx="40" starty="1" priority="149"/> |
| 5177 | + <!--Column of 'M9K' with 'EMPTY' blocks wherever a 'M9K' does not fit. Vertical offset by 1 for perimeter.--> |
| 5178 | + <col type="M9K" startx="5" starty="2" repeatx="26" priority="50"/> |
| 5179 | + <col type="EMPTY" startx="5" repeatx="26" starty="1" priority="49"/> |
| 5180 | + <!--Column of 'M144K' with 'EMPTY' blocks wherever a 'M144K' does not fit. Vertical offset by 1 for perimeter.--> |
| 5181 | + <col type="M144K" startx="33" starty="2" repeatx="43" priority="100"/> |
| 5182 | + <col type="EMPTY" startx="33" repeatx="43" starty="1" priority="99"/> |
| 5183 | + </layer> |
| 5184 | + </fixed_layout> |
5051 | 5185 | <!--
|
5052 | 5186 | Stratix IV has only 4 unique device dies.
|
5053 | 5187 | Some devices are 'virtual': based off another die, with utilization limits controlled by Quartus
|
|
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