diff --git a/README.developers.md b/README.developers.md index da209dff72f..92e59ac8614 100644 --- a/README.developers.md +++ b/README.developers.md @@ -534,40 +534,117 @@ The [Koios benchmarks](https://github.com/verilog-to-routing/vtr-verilog-to-rout The are provided as synthesizable verilog and can be re-mapped to VTR supported architectures. They consist mostly of medium to large sized circuits from Deep Learning (DL). They can be used for FPGA architecture exploration for DL and also for tuning CAD tools. -A typical approach to evaluating an algorithm change would be to run `koios` (or `koios_no_complex_dsp`) task from the nightly regression test (vtr_reg_nightly_test6) and the `koios` (or `koios_no_complex_dsp`) task from the weekly regression test (vtr_reg_weekly). The nightly test contains smaller benchmarks, whereas the large designs are in the weekly regression test. To measure QoR for the entire benchmark suite, both nightly and weekly tests should be run and the results should be concatenated. +A typical approach to evaluating an algorithm change would be to run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4), the `koios_large` (or `koios_large_no_hb`) and the `koios_proxy` (or `koios_proxy_no_hb`) tasks from the weekly regression test (vtr_reg_weekly). The nightly test contains smaller benchmarks, whereas the large designs are in the weekly regression test. To measure QoR for the entire benchmark suite, both nightly and weekly tests should be run and the results should be concatenated. -The `koios` regression task runs these benchmarks with complex_dsp functionality enabled, whereas `koios_no_complex_dsp` regression task runs these benchmarks without complex_dsp functionality. Normally, only the `koios` tasks should be enough for QoR. +For evaluating an algorithm change in the Odin frontend, run `koios_medium` (or `koios_medium_no_hb`) tasks from the nightly regression test (vtr_reg_nightly_test4_odin) and the `koios_large_odin` (or `koios_large_no_hb_odin`) tasks from the weekly regression test (vtr_reg_weekly). -The following steps show a sequence of commands to run the `koios` tasks on the Koios benchmarks from both nightly and weekly regressions: +The `koios_medium`, `koios_large`, and `koios_proxy` regression tasks run these benchmarks with complex_dsp functionality enabled, whereas `koios_medium_no_hb`, `koios_large_no_hb` and `koios_proxy_no_hb` regression tasks run these benchmarks without complex_dsp functionality. Normally, only the `koios_medium`, `koios_large`, and `koios_proxy` tasks should be enough for QoR. + +The `koios_sv` and `koios_sv_no_hb` tasks utilize the System-Verilog parser in the Parmys frontend. + +The following table provides details on available Koios settings in VTR flow: +| Suite |Test Description | Target | Complex DSP Features | Config file | Frontend | Parser | +|---------------|----------------------|---------------|---------------|---------------|---------------|---------------| +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4/koios_medium | Parmys | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4/koios_medium_no_hb | Parmys | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4_odin/koios_medium | Odin | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4_odin/koios_medium_no_hb | Odin | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large_odin | Odin | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb_odin | Odin | | +| Weekly | Proxy designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_proxy | Parmys | | +| Weekly | Proxy designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_proxy_no_hb | Parmys | | +| Weekly | deepfreeze designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_sv | Parmys | System-Verilog | +| Weekly | deepfreeze designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_sv_no_hb | Parmys | System-Verilog | + +For more information refer to the [Koios benchmark home page](vtr_flow/benchmarks/verilog/koios/README.md). + +The following steps show a sequence of commands to run the `koios` tasks on the Koios benchmarks: ```shell #From the VTR root $ cd vtr_flow/tasks -#Run the VTR benchmarks -$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_nightly_test6/koios & -$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios & +#Choose any config file from the table above and run the Koios benchmarks, for example: +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_large & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv & + +#Disable hard blocks (hard_mem and complex_dsp macros) to verify memory and generic hard blocks inference: +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_large_no_hb & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy_no_hb & +$ ../scripts/run_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb & #Several hours later... they complete #Parse the results -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test6/koios -$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv + +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_large_no_hb +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_proxy_no_hb +$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_weekly/koios_sv_no_hb #The run directory should now contain a summary parse_results.txt file -$ head -5 vtr_reg_nightly_test6/koios//parse_results.txt -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.v common 2871.10 9.36 235096 5 619.21 -1 -1 159760 -1 -1 1119 355 14 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 2568860 355 289 50215 41827 2 23224 2053 136 136 18496 dsp_top auto 1233.72 457725 91.70 0.38 7.24742 -105267 -7.24742 2.59789 14.13 0.101267 0.0738583 24.91 18.6865 -1 561916 17 5.92627e+08 1.03195e+08 4.09037e+08 22114.9 16.37 32.3744 25.1979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 7527.41 42.24 729876 5 3941.31 -1 -1 630244 -1 -1 5545 194 828 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 4409476 194 13 217044 174718 1 91037 6708 164 164 26896 memory auto 1604.22 969627 663.41 2.84 5.61569 -424718 -5.61569 5.61569 21.49 0.584073 0.385993 104.796 73.1698 -1 1450542 14 8.6211e+08 3.01197e+08 5.93540e+08 22068.0 53.97 132.203 96.049 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 2028.52 40.37 577472 3 240.94 -1 -1 513656 -1 -1 5695 260 0 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 2195980 260 122 231647 179602 1 86181 6140 83 83 6889 clb auto 613.32 940951 503.35 2.87 6.4402 -131403 -6.4402 6.4402 5.41 0.753268 0.564332 85.331 60.8639 -1 1224690 16 2.13666e+08 1.74902e+08 1.51359e+08 21971.1 50.49 114.382 84.8538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1330.99 11.83 1095592 7 59.16 -1 -1 560612 -1 -1 1248 1058 161 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 1180420 1058 16 47407 39134 1 26605 2588 86 86 7396 dsp_top auto 728.70 234151 118.11 0.71 5.89837 -78343.6 -5.89837 5.89837 6.64 0.181478 0.146942 31.9659 24.5807 -1 366899 17 2.32446e+08 8.36361e+07 1.62201e+08 21930.9 16.25 40.6352 32.1556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - -$ head -5 vtr_reg_weekly/koios//parse_results.txt -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 19316.21 162.86 2395612 3 15651.23 -1 -1 1337084 -1 -1 9309 293 407 -1 success v8.0.0-4470-ge625fdfe9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-06-18T14:02:07 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 4793656 293 290 374045 333664 1 99618 10661 152 152 23104 dsp_top auto 780.11 1482046 931.17 6.18 6.93257-474705 -6.93257 6.93257 27.96 1.30491 1.10886 193.621 147.02 -1 1762769 16 7.41832e+08 4.07655e+08 5.09972e+08 22072.9 106.48 263.016 205.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 66156.51 483.84 4490632 3 60586.75 -1 -1 2480684 -1 -1 17641 293 784 -1 success v8.0.0-4470-ge625fdfe9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-06-18T14:02:07 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 8819072 293 578 696105 624609 1 181497 19958 206 206 42436 dsp_top auto 1057.61 3181171 1581.42 7.89 8.18417-1.24303e+06 -8.18417 8.18417 38.05 1.40496 0.993779 233.672 173.509 -1 3532357 18 1.36407e+09 7.68183e+08 9.34572e+08 22023.1 165.78 317.679 246.098 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 101695.32 717.44 6547568 3 94597.42 -1 -1 3590044 -1 -1 25995 293 1161 -1 success v8.0.0-4470-ge625fdfe9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-06-18T14:02:07 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 13040176 293 866 1018158 915547 1 263328 29277 248 248 61504 dsp_top auto 1503.62 5185716 1951.96 10.18 8.86387-1.97516e+06 -8.86387 8.86387 46.08 1.71937 1.21506 288.67 213.718 -1 5523775 18 1.98856e+09 1.12933e+09 1.35238e+09 21988.4 224.14 391.303 303.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 38901.96 35.76 651868 7 30532.88 -1 -1 606240 -1 -1 6626 17 305 -1 success v8.0.0-4470-ge625fdfe9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-06-18T14:02:07 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 6036204 17 19 252939 204226 1 121211 7577 200 200 40000 dsp_top auto 4576.24 1453809 1136.46 3.95 8.38544 -386636 -8.385448.38544 54.87 0.944433 0.763732 237.758 176.282 -1 1876011 15 1.28987e+09 3.81683e+08 8.80433e+08 22010.877.53 284.979 214.902 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +$ head -5 vtr_reg_nightly_test4/koios_medium//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 677.72 vpr 2.29 GiB -1 -1 19.40 195276 5 99.61 -1 -1 109760 -1 -1 492 355 32 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2400616 355 289 25429 18444 2 12313 1433 136 136 18496 dsp_top auto 208.3 MiB 14.61 359754 2344.4 MiB 16.75 0.18 5.12303 -82671.4 -5.12303 2.1842 6.09 0.0412666 0.0368158 6.35102 5.65512 -1 394367 16 5.92627e+08 8.53857e+07 4.08527e+08 22087.3 4.50 8.69097 7.85207 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 722.22 vpr 2.30 GiB -1 -1 23.09 242848 5 72.60 -1 -1 117236 -1 -1 686 357 58 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2415672 357 289 25686 20353 2 12799 1656 136 136 18496 dsp_top auto 233.3 MiB 98.40 226648 2359.1 MiB 20.07 0.17 8.31923 -74283.8 -8.31923 2.78336 6.05 0.0420585 0.0356747 6.53862 5.54952 -1 293644 13 5.92627e+08 9.4632e+07 4.08527e+08 22087.3 4.58 8.69976 7.55132 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 2800.18 vpr 1.75 GiB -1 -1 94.38 736748 6 754.09 -1 -1 389988 -1 -1 3895 206 132 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1840088 206 13 165036 139551 1 69732 4358 88 88 7744 dsp_top auto 1052.4 MiB 1692.76 601396 1606.1 MiB 88.48 0.64 5.30279 -150931 -5.30279 5.30279 1.96 0.131322 0.104184 16.7561 13.7761 -1 876475 15 2.4541e+08 1.55281e+08 1.69370e+08 21871.2 14.42 24.7943 21.0377 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 797.74 vpr 2.01 GiB -1 -1 84.28 729308 3 56.57 -1 -1 411036 -1 -1 6190 260 0 -1 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2106860 260 122 206251 154342 1 87361 6635 87 87 7569 clb auto 1300.8 MiB 202.79 910701 1723.3 MiB 174.17 1.12 6.77966 -140235 -6.77966 6.77966 1.97 0.198989 0.175034 29.926 24.7241 -1 1199797 17 2.37162e+08 1.88714e+08 1.65965e+08 21927.0 20.72 41.872 35.326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_large//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 6320.39 parmys 6.81 GiB -1 -1 2279.37 7141128 8 3659.89 -1 -1 229600 -1 -1 1215 3 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 406996 3 73 29130 23346 1 13644 1292 40 40 1600 clb auto 246.6 MiB 64.06 136280 627318 185500 408250 33568 357.7 MiB 81.14 0.66 8.27929 -16089.3 -8.27929 8.27929 1.10 0.16804 0.146992 16.9432 13.6451 -1 224227 19 4.87982e+07 3.41577e+07 3.42310e+07 21394.3 19.75 26.6756 21.8374 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 11605.17 vpr 3.24 GiB -1 -1 669.16 1080564 4 7868.39 -1 -1 606244 -1 -1 7733 652 237 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3400468 652 290 299247 274102 1 72966 9121 120 120 14400 dsp_top auto 1946.1 MiB 741.62 1061263 13535473 5677109 7516142 342222 3001.0 MiB 915.91 6.25 6.0577 -397722 -6.0577 6.0577 16.74 1.09797 0.908781 169.318 135.356 -1 1289121 17 4.60155e+08 3.01448e+08 3.17281e+08 22033.4 108.23 234.326 190.185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 42560.88 vpr 6.35 GiB -1 -1 1060.82 2104648 4 35779.24 -1 -1 1168924 -1 -1 15289 652 458 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6658128 652 578 587833 538751 1 142046 17388 168 168 28224 dsp_top auto 3792.2 MiB 1334.50 2402446 32440572 13681743 17973716 785113 5856.8 MiB 1927.66 10.89 6.9964 -921673 -6.9964 6.9964 34.97 2.51671 1.97649 373.17 302.896 -1 2735850 16 9.07771e+08 5.93977e+08 6.21411e+08 22017.1 228.75 493.742 407.089 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 79534.09 vpr 9.24 GiB -1 -1 1581.99 3213072 4 69583.96 -1 -1 1763048 -1 -1 22846 652 679 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9688232 652 866 876458 803425 1 211260 25656 200 200 40000 dsp_top auto 5580.4 MiB 2073.77 4237568 55245338 23267923 30805131 1172284 8437.3 MiB 2868.84 15.36 8.07111 -1.60215e+06 -8.07111 8.07111 54.87 2.67554 2.06921 438.894 351.141 -1 4656710 14 1.28987e+09 8.86534e+08 8.79343e+08 21983.6 469.61 576.631 470.505 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_proxy//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.1.v common 30535.22 vpr 9.48 GiB -1 -1 1652.38 3799616 7 2393.26 -1 -1 771680 -1 -1 5817 938 845 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 9940848 938 175 262404 208705 1 137273 8816 264 264 69696 dsp_top auto 1962.1 MiB 17465.99 3242084 14209964 6064078 7558347 587539 9707.9 MiB 2269.49 11.20 8.49902 -576590 -8.49902 8.49902 120.99 1.65144 1.34401 319.238 263.953 -1 4269357 15 2.25492e+09 5.42827e+08 1.53035e+09 21957.6 291.49 414.451 348.422 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.2.v common 49383.26 parmys 7.46 GiB -1 -1 6711.91 7820216 8 22879.15 -1 -1 1478720 -1 -1 8948 318 1105 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 6046424 318 256 373725 328044 1 148054 10957 188 188 35344 memory auto 2466.3 MiB 15021.62 2653372 16311253 6713874 9344147 253232 5904.7 MiB 1439.25 8.76 7.35195 -768561 -7.35195 7.35195 47.97 1.45054 1.22978 225.237 181.257 -1 3431386 18 1.1352e+09 4.85551e+08 7.77871e+08 22008.6 262.44 314.625 258.401 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.3.v common 19852.09 vpr 4.44 GiB -1 -1 2415.20 2344724 9 11508.95 -1 -1 604164 -1 -1 9318 732 846 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 4650536 732 304 284977 256401 1 127990 11307 164 164 26896 memory auto 2050.2 MiB 1517.07 1834702 15487251 6133696 9051915 301640 4541.5 MiB 1750.28 13.38 9.89252 -499927 -9.89252 9.89252 33.45 1.83357 1.60237 215.923 175.904 -1 2500777 18 8.6211e+08 4.03628e+08 5.92859e+08 22042.6 191.91 301.651 247.975 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_sv//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style1.sv common 22714.73 vpr 4.09 GiB -1 -1 949.56 2651192 3 16835.50 -1 -1 1290132 -1 -1 12293 27 396 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 4288252 27 513 420409 319910 1 173122 13274 122 122 14884 clb auto 2706.3 MiB 2229.92 358719 32218159 15492330 11108513 5617316 3575.6 MiB 1036.24 4.96 4.77742 -203483 -4.77742 4.77742 16.43 1.44734 1.24291 322.276 265.06 -1 525106 18 4.7523e+08 4.08959e+08 3.28149e+08 22047.1 89.42 403.175 333.904 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style2.sv common 24680.43 vpr 14.80 GiB -1 -1 827.06 2325884 3 11919.13 -1 -1 1064952 -1 -1 8475 6 140 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 15515036 6 513 281129 194945 1 142714 10896 338 338 114244 dsp_top auto 2163.1 MiB 2308.76 1873008 23434650 9090338 12891091 1453221 15151.4 MiB 1246.22 10.86 11.0869 -410426 -11.0869 11.0869 189.96 1.47102 1.33008 298.642 263.028 -1 2267430 14 3.68993e+09 7.02925e+08 2.50989e+09 21969.6 104.21 368.851 326.754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style3.sv common 9459.64 parmys 2.59 GiB -1 -1 1046.45 2716236 3 5554.19 -1 -1 1151548 -1 -1 4951 27 115 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 2669896 27 513 162561 120322 1 71039 5820 120 120 14400 dsp_top auto 1254.2 MiB 874.69 253375 9948140 4723336 3618748 1606056 2607.3 MiB 379.75 1.99 5.71612 -91795.4 -5.71612 5.71612 14.90 0.558622 0.482091 114.978 97.3208 -1 365131 15 4.60155e+08 2.08293e+08 3.17281e+08 22033.4 34.50 143.778 122.884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_nightly_test4/koios_medium_no_hb//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 2297.73 vpr 2.39 GiB -1 -1 67.66 248916 5 386.57 -1 -1 139588 -1 -1 1092 355 32 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2505488 355 289 47792 39479 2 22463 2033 136 136 18496 dsp_top auto 315.6 MiB 829.80 417547 2035967 800879 1110613 124475 2446.8 MiB 59.61 0.36 7.56032 -98878.8 -7.56032 2.65337 18.45 0.123782 0.101211 21.3991 17.4955 -1 526122 14 5.92627e+08 1.02128e+08 4.08527e+08 22087.3 15.74 27.6882 23.1868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 2034.94 vpr 2.43 GiB -1 -1 56.02 302204 5 517.89 -1 -1 139816 -1 -1 1447 357 58 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2549132 357 289 56236 49095 2 21896 2417 136 136 18496 dsp_top auto 393.4 MiB 344.10 429105 2548015 930606 1466225 151184 2489.4 MiB 85.48 0.50 7.79199 -137248 -7.79199 2.69372 18.37 0.163784 0.137256 28.7844 22.9255 -1 558155 17 5.92627e+08 1.15867e+08 4.08527e+08 22087.3 23.93 38.6761 31.6913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 8355.37 vpr 1.83 GiB -1 -1 172.77 753612 6 2243.64 -1 -1 412976 -1 -1 4119 206 132 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 1920604 206 13 177171 148374 1 74857 4582 88 88 7744 dsp_top auto 1112.1 MiB 5121.00 676743 4607543 1735144 2771118 101281 1657.7 MiB 309.31 2.26 6.5785 -161896 -6.5785 6.5785 6.26 0.492287 0.382534 63.1824 50.6687 -1 975264 23 2.4541e+08 1.61532e+08 1.69370e+08 21871.2 57.11 95.977 78.7754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1618.20 vpr 2.03 GiB -1 -1 148.99 734288 3 121.88 -1 -1 410764 -1 -1 6192 260 0 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2131528 260 122 206267 154358 1 87325 6637 87 87 7569 clb auto 1304.8 MiB 399.50 897507 7862107 3019050 4332770 510287 1741.6 MiB 424.98 3.12 6.46586 -141256 -6.46586 6.46586 5.97 0.627132 0.490712 79.1961 63.5977 -1 1180668 18 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 60.49 113.428 92.6149 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_large_no_hb//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 6512.03 parmys 6.81 GiB -1 -1 2803.15 7141204 8 3272.22 -1 -1 229632 -1 -1 1215 3 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 406888 3 73 29130 23346 1 13644 1292 40 40 1600 clb auto 246.5 MiB 63.14 136280 627318 185500 408250 33568 357.6 MiB 85.00 0.86 8.27929 -16089.3 -8.27929 8.27929 1.13 0.12917 0.113598 13.8302 11.3301 -1 224227 19 4.87982e+07 3.41577e+07 3.42310e+07 21394.3 19.69 22.8327 18.7232 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 17199.48 vpr 3.24 GiB -1 -1 583.78 1084852 4 13572.40 -1 -1 606412 -1 -1 7731 652 237 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3400564 652 290 299239 274094 1 72874 9119 120 120 14400 dsp_top auto 1946.4 MiB 725.17 1086525 13721951 5750436 7628104 343411 3000.6 MiB 920.88 5.92 6.3706 -404576 -6.3706 6.3706 16.00 1.30631 1.07494 208.425 167.37 -1 1308179 19 4.60155e+08 3.01393e+08 3.17281e+08 22033.4 125.07 285.633 232.404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 44836.58 vpr 6.35 GiB -1 -1 1206.67 2108616 4 37270.70 -1 -1 1168924 -1 -1 15290 652 460 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6654212 652 578 587830 538748 1 142127 17391 168 168 28224 dsp_top auto 3784.4 MiB 1272.33 2541145 33348915 14048448 18476269 824198 5852.2 MiB 2378.39 15.56 6.83162 -1.04508e+06 -6.83162 6.83162 36.38 2.58887 2.22298 379.541 301.913 -1 2865108 16 9.07771e+08 5.9428e+08 6.21411e+08 22017.1 283.80 506.773 410.065 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 79425.36 vpr 9.26 GiB -1 -1 1997.66 3183680 4 68911.59 -1 -1 1763240 -1 -1 22848 652 682 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9708760 652 866 876471 803438 1 211268 25661 200 200 40000 dsp_top auto 5596.5 MiB 2037.93 4249390 55259651 23005638 31099607 1154406 8453.4 MiB 2762.94 28.11 7.65321 -1.56393e+06 -7.65321 7.65321 50.04 2.65623 2.07346 405.053 322.505 -1 4619796 15 1.28987e+09 8.87003e+08 8.79343e+08 21983.6 963.02 568.098 461.604 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_proxy_no_hb//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.1.v common 30535.22 vpr 9.48 GiB -1 -1 1652.38 3799616 7 2393.26 -1 -1 771680 -1 -1 5817 938 845 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 9940848 938 175 262404 208705 1 137273 8816 264 264 69696 dsp_top auto 1962.1 MiB 17465.99 3242084 14209964 6064078 7558347 587539 9707.9 MiB 2269.49 11.20 8.49902 -576590 -8.49902 8.49902 120.99 1.65144 1.34401 319.238 263.953 -1 4269357 15 2.25492e+09 5.42827e+08 1.53035e+09 21957.6 291.49 414.451 348.422 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.2.v common 49383.26 parmys 7.46 GiB -1 -1 6711.91 7820216 8 22879.15 -1 -1 1478720 -1 -1 8948 318 1105 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 6046424 318 256 373725 328044 1 148054 10957 188 188 35344 memory auto 2466.3 MiB 15021.62 2653372 16311253 6713874 9344147 253232 5904.7 MiB 1439.25 8.76 7.35195 -768561 -7.35195 7.35195 47.97 1.45054 1.22978 225.237 181.257 -1 3431386 18 1.1352e+09 4.85551e+08 7.77871e+08 22008.6 262.44 314.625 258.401 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.3.v common 19852.09 vpr 4.44 GiB -1 -1 2415.20 2344724 9 11508.95 -1 -1 604164 -1 -1 9318 732 846 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 4650536 732 304 284977 256401 1 127990 11307 164 164 26896 memory auto 2050.2 MiB 1517.07 1834702 15487251 6133696 9051915 301640 4541.5 MiB 1750.28 13.38 9.89252 -499927 -9.89252 9.89252 33.45 1.83357 1.60237 215.923 175.904 -1 2500777 18 8.6211e+08 4.03628e+08 5.92859e+08 22042.6 191.91 301.651 247.975 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.4.v common 54152.82 parmys 8.16 GiB -1 -1 5711.77 8560300 7 7695.81 -1 -1 1228588 -1 -1 7685 546 1085 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 7638244 546 1846 328200 285098 1 145315 11924 222 222 49284 dsp_top auto 2318.8 MiB 34102.96 3359643 20028032 8510897 11052028 465107 7459.2 MiB 2454.78 12.61 9.3047 -839575 -9.3047 9.3047 72.17 2.37032 2.07569 353.073 294.754 -1 4470327 15 1.58612e+09 5.57186e+08 1.08358e+09 21986.5 321.00 457.912 387.485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + +$ head -5 vtr_reg_weekly/koios_sv_no_hb//parse_results.txt +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style1.sv common 47967.94 vpr 10.31 GiB -1 -1 1750.70 3477528 3 33798.52 -1 -1 1967140 -1 -1 20253 27 1843 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 10811692 27 513 778797 600279 1 384107 23186 244 244 59536 memory auto 4968.5 MiB 3724.68 4867625 48601541 21188063 25604799 1808679 10366.4 MiB 3892.48 41.19 8.46401 -1.13947e+06 -8.46401 8.46401 82.35 2.83854 2.28574 443.492 355.56 -1 5791588 17 1.92066e+09 9.58441e+08 1.30834e+09 21975.7 419.89 594.451 484.887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style2.sv common 48524.73 vpr 8.29 GiB -1 -1 1440.31 3118316 3 35219.69 -1 -1 1725016 -1 -1 22674 27 1231 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 8696204 27 513 757966 564979 1 371413 24999 196 196 38416 memory auto 4726.6 MiB 2712.89 5184470 52271336 22299033 27769653 2202650 7642.4 MiB 5209.27 55.51 9.75062 -937734 -9.75062 9.75062 50.02 2.30465 1.94566 366.253 293.69 -1 6516523 17 1.23531e+09 9.4276e+08 8.45266e+08 22003.0 925.98 493.024 402.412 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style3.sv common 41631.02 vpr 15.22 GiB -1 -1 1622.97 3431784 3 24896.76 -1 -1 1856148 -1 -1 20779 27 3333 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 15958564 27 513 703297 547641 1 350325 24854 324 324 104976 memory auto 4656.9 MiB 3861.23 5201129 61655974 26414908 31818866 3422200 15584.5 MiB 3575.85 19.40 9.71561 -1.53645e+06 -9.71561 9.71561 179.24 2.62795 2.23108 484.893 395.834 -1 6173057 19 3.39753e+09 1.08992e+09 2.30538e+09 21961.0 377.21 640.096 530.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + ``` ### Example: Extracting QoR Data from CI Runs diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 04140579c07..0cb127387ab 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -32,6 +32,7 @@ if (${WITH_PARMYS}) GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git GIT_TAG v1.71 GIT_PROGRESS TRUE + GIT_SHALLOW TRUE # setting source, build and install directories SOURCE_DIR "${SURELOG_SOURCE_DIR}" @@ -49,7 +50,7 @@ if (${WITH_PARMYS}) LOG_BUILD ON LOG_UPDATE ON LOG_INSTALL ON - LOG_CONFIGURE ON + LOG_CONFIGURE OFF LOG_OUTPUT_ON_FAILURE ON # dependency @@ -63,6 +64,7 @@ if (${WITH_PARMYS}) GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git GIT_TAG v1.20230808 GIT_PROGRESS TRUE + GIT_SHALLOW TRUE # setting source, build and install directories SOURCE_DIR "${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}" @@ -82,7 +84,7 @@ if (${WITH_PARMYS}) LOG_BUILD ON LOG_UPDATE ON LOG_INSTALL ON - LOG_CONFIGURE ON + LOG_CONFIGURE OFF LOG_OUTPUT_ON_FAILURE ON # dependency diff --git a/vtr_flow/benchmarks/system_verilog/koios_sv/README.md b/vtr_flow/benchmarks/system_verilog/koios_sv/README.md new file mode 100644 index 00000000000..f1d24e85c06 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/koios_sv/README.md @@ -0,0 +1,2 @@ +# SV_benchmarks +Koios Benchmarks for FPGA Research with SystemVerilog features diff --git a/vtr_flow/benchmarks/verilog/koios/deepfreeze.style1.sv b/vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style1.sv similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/deepfreeze.style1.sv rename to vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style1.sv diff --git a/vtr_flow/benchmarks/verilog/koios/deepfreeze.style2.sv b/vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style2.sv similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/deepfreeze.style2.sv rename to vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style2.sv diff --git a/vtr_flow/benchmarks/verilog/koios/deepfreeze.style3.sv b/vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style3.sv similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/deepfreeze.style3.sv rename to vtr_flow/benchmarks/system_verilog/koios_sv/deepfreeze.style3.sv diff --git a/vtr_flow/benchmarks/verilog/koios/README.md b/vtr_flow/benchmarks/verilog/koios/README.md index 9563fab5c1d..67068c1eed1 100644 --- a/vtr_flow/benchmarks/verilog/koios/README.md +++ b/vtr_flow/benchmarks/verilog/koios/README.md @@ -13,7 +13,7 @@ Koios benchmarks use advanced DSP features that are available in only a few FPGA Similarly, Koios benchmark instantiate hard memory blocks (single port and dual port BRAM). These blocks are available in most architectures provided with VTR, but may not be available in a user's architecture. These hard memory blocks can be controlled by using the macro ``hard_mem``. If `hard_mem` is defined in a benchmark file (using `` `define hard_mem``), then hard memory blocks will be used. If `hard_mem` is not defined, then equivalent functionality is obtained through behavioral Verilog that the synthesis tools can automatically infer as RAMs. -From a flow perspective, you can enable/disable a macro (like `complex_dsp`) without actually modifying the benchmark file(s). You can specify a separate Verilog header file while running a flow/task that contains these macros. For `run_vtr_flow` users, `-include ` needs to be added. For `run_vtr_task` users, `includes_dir` and `include_list_add` need to be specified in the task file. An example task file can be seen [here](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt). +From a flow perspective, you can enable/disable a macro (like `complex_dsp`) without actually modifying the benchmark file(s). You can specify a separate Verilog header file while running a flow/task that contains these macros. For `run_vtr_flow` users, `-include ` needs to be added. For `run_vtr_task` users, `includes_dir` and `include_list_add` need to be specified in the task file. An example task file can be seen [here](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/vtr_reg_basic/hdl_include/config/config.txt). Using hard macros for DSPs and BRAMs to utilize advanced features (like chaining) is common in modern designs used with contemporary FPGAs. When using these benchmarks and enabling these advanced features, an FPGA architecture that supports these features must be provided. Supporting these features implies that the architecture XML file provided to VTR must describe such features (e.g. by defining a hard block macro DSP slice). We provide such architectures with Koios. The FPGA architectures with advanced DSP that work out-of-the-box with Koios benchmarks are available here: @@ -29,17 +29,41 @@ If users want to use a different FPGA architecture file, they can replace the ma ## Proxy benchmarks In Koios 2.0, there are 8 synthetic/proxy benchmarks. These were generated using a framework that is present [here](https://github.com/UT-LCA/koios_proxy_benchmarks). To generate more benchmarks using this framework, use the generate_benchmark.py script. +## SystemVerilog benchmarks +In Koios, there are 3 system-verilog benchmarks. These are based on ARM FixyNN DeepFreeze and accelerate some layers of MobileNet. + ## Regressions -Koios benchmarks are tested by the following regression tests in VTR: -| Suite |Test Description | Config file | Wall-clock time | -|---------------|----------------------|---------------|-------------------| -| Strong | A test circuit. Goal is to check the architecture files. | tasks/regression_tests/vtr_reg_strong/koios | 6 seconds | -| Strong | Same test circuit without enabling complex dsp features | tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp | 6 seconds| -| Nightly | Small-to-medium sized designs from Koios run with one arch file | tasks/regression_tests/vtr_reg_nightly_test6/koios | 2 hours with -j3 | -| Nightly | Small-to-medium sized designs from Koios run with an arch file without enabling complex dsp features | tasks/regression_tests/vtr_reg_nightly_test6/koios_no_complex_dsp | 2 hours with -j3 | -| Nightly | A small design from Koios run with various flavors of the arch file that enables complex dsp features | tasks/regression_tests/vtr_reg_nightly_test6/koios_multi_arch | 2 hours with -j3 | -| Weekly | Large designs from Koios run with one arch file | tasks/regression_tests/vtr_reg_weekly/koios | a little over 24 hours with -j4 | -| Weekly | Large designs from Koios run with an arch file without enabling complex dsp features | tasks/regression_tests/vtr_reg_weekly/koios_no_complex_dsp | a little over 24 hours with -j4 | +Koios benchmarks are tested by the following tasks in VTR: +| Suite |Test Description | Target | Complex DSP Features | Config file | Frontend | Parser | +|---------------|----------------------|---------------|---------------|---------------|---------------|---------------| +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4/koios_medium | Parmys | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4/koios_medium_no_hb | Parmys | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test4_odin/koios_medium | Odin | | +| Nightly | Medium designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test4_odin/koios_medium_no_hb | Odin | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb | Parmys | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_large_odin | Odin | | +| Weekly | Large designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_large_no_hb_odin | Odin | | +| Weekly | Proxy designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_proxy | Parmys | | +| Weekly | Proxy designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_proxy_no_hb | Parmys | | +| Weekly | deepfreeze designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_sv | Parmys | System-Verilog | +| Weekly | deepfreeze designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_weekly/koios_sv_no_hb | Parmys | System-Verilog | + +The following are only for regression testing and less important for benchmarking: +| Suite |Test Description | Target | Complex DSP Features | Config file | Frontend | +|---------------|----------------------|---------------|---------------|---------------|---------------| +| Strong | A test circuit to check the architecture file | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_strong/koios_test | Parmys | +| Strong | Same test circuit without hard blocks | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_strong/koios_test_no_hb | Parmys | +| Strong | A test circuit to check the architecture file | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_strong_odin/koios_test | Odin | +| Strong | Same test circuit without hard blocks | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_strong_odin/koios_test_no_hb | Odin | +| Nightly | The `conv_layer.v` design | multiple | ✓ | vtr_reg_nightly_test4/koios_medium_multi_arch | Parmys | +| Nightly | The `conv_layer.v` design | multiple | ✓ | vtr_reg_nightly_test4_odin/koios_medium_multi_arch | Odin | +| Nightly | Other designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_nightly_test6/koios_other | Parmys | +| Nightly | Other designs | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | | vtr_reg_nightly_test6/koios_other_no_hb | Parmys | +| Nightly | The `bwave_like.fixed.small.v` design | multiple | ✓ | vtr_reg_nightly_test6/koios_other_multi_arch | Parmys | +| Weekly | The `dla_like.large.v` design | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_dla_large | Parmys | +| Weekly | The `bwave_like.float.large.v` design | k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml | ✓ | vtr_reg_weekly/koios_bwave_float_large | Parmys | | + ## Collecting QoR measurements For collecting QoR measurements on Koios benchmarks, follow the instructions [here](https://docs.verilogtorouting.org/en/latest/README.developers/#example-koios-benchmarks-qor-measurement). diff --git a/vtr_flow/benchmarks/verilog/koios_proxy/README.md b/vtr_flow/benchmarks/verilog/koios_proxy/README.md new file mode 100644 index 00000000000..098609d2de5 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios_proxy/README.md @@ -0,0 +1,4 @@ +# proxy_benchmarks +Generate Synthetic Benchmarks for FPGA Research + +More information: [koios_proxy_benchmarks](https://github.com/UT-LCA/koios_proxy_benchmarks.git) \ No newline at end of file diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.1.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.1.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.1.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.1.v index b12b06e983b..1baa2bbe2dc 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.1.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.1.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [935:0] top_inp, output [174:0] top_outp); @@ -5404,7 +5397,7 @@ end endmodule -module interface_14(input [2545:0] inp, output [2519:0] outp, input clk, input reset); +module interface_14(input [2545:0] inp, output reg [2519:0] outp, input clk, input reset); reg [2545:0]intermediate_reg_0; always@(posedge clk) begin intermediate_reg_0 <= inp; @@ -6688,10 +6681,10 @@ xor_module xor_module_inst_1_1272(.clk(clk),.reset(reset),.i1(intermediate_reg_0 wire [1271:0]intermediate_wire_2; assign intermediate_wire_2[1271] = intermediate_reg_1[1272]^intermediate_reg_1[1271] ; assign intermediate_wire_2[1270:0] = intermediate_reg_1[1270:0] ; -//always@(posedge clk) begin -assign outp [1271:0] = intermediate_wire_2; -assign outp[2519:1272] = intermediate_wire_2[1247:0] ; -//end +always@(posedge clk) begin +outp [1271:0] <= intermediate_wire_2; +outp[2519:1272] <= intermediate_wire_2[1247:0] ; +end endmodule @@ -19309,7 +19302,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -19475,6 +19468,8 @@ reg [18:0] ay_reg; reg [17:0] bx_reg; reg [18:0] by_reg; reg [36:0] resulta_reg; +reg [36:0] resultaxy_reg; +reg [36:0] resultbxy_reg; always @(posedge clk) begin if(reset) begin resulta_reg <= 0; @@ -19488,7 +19483,9 @@ always @(posedge clk) begin ay_reg <= ay; bx_reg <= bx; by_reg <= by; - resulta_reg <= ax_reg * ay_reg + bx_reg * by_reg + chainin; + resultaxy_reg <= ax_reg * ay_reg; + resultbxy_reg <= bx_reg * by_reg; + resulta_reg <= resultaxy_reg + resultbxy_reg + chainin; end end assign resulta = resulta_reg; @@ -19520,7 +19517,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -20474,7 +20471,7 @@ module fifo_512_40bit (clk, rst, clr, din, we, dout, re, full, empty); -localparam max_size = 1<= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd3; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd4; end 4'b0001:begin @@ -21471,7 +21476,7 @@ begin address = 5'd12; else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd13; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd14; end 4'b0010:begin @@ -21487,7 +21492,7 @@ begin address = 5'd19; else if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) address = 5'd20; - else + else if(x_comp[11:0] >= 16'h99a) address = 5'd21; end default: address = 0; @@ -21498,7 +21503,7 @@ begin begin address = 5'd23; end - else + else //else if(x_comp >= 16'h3000) begin address = 5'd22; @@ -21625,7 +21630,7 @@ begin begin address = 6'd11; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd12; end @@ -21645,7 +21650,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -21665,7 +21670,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -21685,7 +21690,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -21705,7 +21710,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -21725,7 +21730,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -21745,7 +21750,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -21772,7 +21777,7 @@ begin 4'b0101: address = lut[46]; 4'b0110: address = lut[46]; 4'b0111: address = lut[46]; */ - default:address = 16'h1000; + default: address = 16'h1000; endcase end @@ -21924,7 +21929,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -22203,4 +22208,3 @@ end end endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.2.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.2.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.2.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.2.v index 1de60b34691..a9a7c6154fd 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.2.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.2.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [315:0] top_inp, output [255:0] top_outp); @@ -31436,7 +31429,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -31651,7 +31644,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -32928,7 +32921,7 @@ assign mux1_out = mux1_select ? cascade_in : data_in; reg [79:0]dot_unit_input_1; // D Flip Flop with reset and enable -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) dot_unit_input_1 <= 0; else if (dot_unit_input_1_enable) dot_unit_input_1 <= data_in; end @@ -32938,7 +32931,7 @@ reg[79:0] bank0_reg0; reg[79:0] bank0_reg1; reg[79:0] bank0_reg2; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin bank0_reg0 <= 0; bank0_reg1 <= 0; @@ -32956,7 +32949,7 @@ reg[79:0] bank1_reg0; reg[79:0] bank1_reg1; reg[79:0] bank1_reg2; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin bank1_reg0 <= 0; bank1_reg1 <= 0; @@ -32994,7 +32987,7 @@ reg [19:0] dot_unit_output_0_flopped; reg [19:0] dot_unit_output_1_flopped; reg [19:0] dot_unit_output_2_flopped; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin dot_unit_output_0_flopped <= 0; dot_unit_output_1_flopped <= 0; @@ -33029,7 +33022,7 @@ assign accumulator_unit1_input1 = accumulator_input1_select[1] ? accumulator_un assign accumulator_unit2_input1 = accumulator_input1_select[2] ? accumulator_unit_output_2_flopped : acc2_in_flopped; // Flopping the accumulator outputs and acc_in -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin accumulator_unit_output_0_flopped <= 0; accumulator_unit_output_1_flopped <= 0; @@ -33262,7 +33255,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -33476,7 +33469,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -33719,7 +33712,7 @@ begin begin address = 6'd11; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd12; end @@ -33739,7 +33732,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -33759,7 +33752,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -33779,7 +33772,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -33799,7 +33792,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -33819,7 +33812,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -33839,7 +33832,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -34140,7 +34133,7 @@ begin address = 5'd2; else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd3; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd4; end 4'b0001:begin @@ -34162,7 +34155,7 @@ begin address = 5'd12; else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd13; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd14; end 4'b0010:begin @@ -34178,7 +34171,7 @@ begin address = 5'd19; else if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) address = 5'd20; - else + else if(x_comp[11:0] >= 16'h99a) address = 5'd21; end default: address = 0; @@ -34201,4 +34194,3 @@ end endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.3.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.3.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.3.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.3.v index 57bc805e927..b4b9f643279 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.3.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.3.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [729:0] top_inp, output [303:0] top_outp); @@ -12628,7 +12621,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -12843,7 +12836,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -13915,7 +13908,7 @@ assign mux1_out = mux1_select ? cascade_in : data_in; reg [79:0]dot_unit_input_1; // D Flip Flop with reset and enable -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) dot_unit_input_1 <= 0; else if (dot_unit_input_1_enable) dot_unit_input_1 <= data_in; end @@ -13925,7 +13918,7 @@ reg[79:0] bank0_reg0; reg[79:0] bank0_reg1; reg[79:0] bank0_reg2; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin bank0_reg0 <= 0; bank0_reg1 <= 0; @@ -13943,7 +13936,7 @@ reg[79:0] bank1_reg0; reg[79:0] bank1_reg1; reg[79:0] bank1_reg2; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin bank1_reg0 <= 0; bank1_reg1 <= 0; @@ -13981,7 +13974,7 @@ reg [31:0] dot_unit_output_0_flopped; reg [31:0] dot_unit_output_1_flopped; reg [31:0] dot_unit_output_2_flopped; -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin dot_unit_output_0_flopped <= 0; dot_unit_output_1_flopped <= 0; @@ -14016,7 +14009,7 @@ assign accumulator_unit1_input1 = accumulator_input1_select[1] ? accumulator_un assign accumulator_unit2_input1 = accumulator_input1_select[2] ? accumulator_unit_output_2_flopped : acc2_in_flopped; // Flopping the accumulator outputs and acc_in -always @ (posedge clk, posedge reset) begin +always @ (posedge clk) begin if (reset == 1'b1) begin accumulator_unit_output_0_flopped <= 0; accumulator_unit_output_1_flopped <= 0; @@ -14447,13 +14440,13 @@ module FPAddSub_a_32( always @(*) begin // Rotate {0 | 4 | 8 | 12} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl2 <= Stage1[23:0]; + 2'b00: Lvl2 <= Stage1[23:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[27:4]; + 2'b01: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end Lvl2[23:19] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[31:8]; + 2'b10: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end Lvl2[23:15] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[35:12]; + 2'b11: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[23:11] <= 0; end endcase end @@ -14475,13 +14468,13 @@ module FPAddSub_a_32( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_2[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[23:0]; + 2'b00: Lvl3 <= Stage2[23:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[24:1]; + 2'b01: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end Lvl3[23] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[25:2]; + 2'b10: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end Lvl3[23:22] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[26:3]; + 2'b11: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end Lvl3[23:21] <= 0; end endcase end @@ -14621,11 +14614,11 @@ module FPAddSub_c_32( // Rotate by 0 2'b00: Lvl2 <= Stage1[32:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[61:29]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[57:25]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[53:21]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -14634,13 +14627,13 @@ module FPAddSub_c_32( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[32:0]; + 2'b00: Lvl3 <= Stage2[32:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[64:32]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[63:31]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[62:30]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -16169,7 +16162,7 @@ FPMult_16_systolic_4x4_fp u_FPMult_16_systolic_4x4_fp( ); //Convert fp16 to fp32 -fp16_to_fp32_systolic_4x4_fp u_16to32 (.clk(clk), .a(FPMult_16_systolic_4x4_fp_result), .b(o_result)); +fp16_to_fp32_systolic_4x4_fp u_16to32 (.a(FPMult_16_systolic_4x4_fp_result), .b(o_result)); endmodule @@ -16545,55 +16538,48 @@ endmodule // A floating point 16-bit to floating point 32-bit converter ////////////////////////////////////////////////////////////////////////// `ifndef complex_dsp -module fp16_to_fp32_systolic_4x4_fp (input clk, input [15:0] a , output [31:0] b); +module fp16_to_fp32_systolic_4x4_fp (input [15:0] a , output [31:0] b); reg [31:0]b_temp; +reg [3:0] j; +reg [3:0] k; reg [3:0] k_temp; +always @ (*) begin -always @ (posedge clk) begin +if ( a [14: 0] == 15'b0 ) begin //signed zero + b_temp [31] = a[15]; //sign bit + b_temp[30:0] = 31'b0; +end + +else begin - if (a[14: 0] == 15'b0) begin //signed zero - b_temp [31] <= a[15]; //sign bit - b_temp[30:0] <= 31'b0; - end else begin - if (a[14:10] == 5'b0) begin //denormalized (covert to normalized) - if (a[9] == 1'b1) begin - k_temp <= 4'd0; - end else if (a[8] == 1'b1) begin - k_temp <= 4'd1; - end else if (a[7] == 1'b1) begin - k_temp <= 4'd2; - end else if (a[6] == 1'b1) begin - k_temp <= 4'd3; - end else if (a[5] == 1'b1) begin - k_temp <= 4'd4; - end else if (a[4] == 1'b1) begin - k_temp <= 4'd5; - end else if (a[3] == 1'b1) begin - k_temp <= 4'd6; - end else if (a[2] == 1'b1) begin - k_temp <= 4'd7; - end else if (a[1] == 1'b1) begin - k_temp <= 4'd8; - end else if (a[0] == 1'b1) begin - k_temp <= 4'd9; - end else begin - k_temp <= 4'd0; + if ( a[14 : 10] == 5'b0 ) begin //denormalized (covert to normalized) + + for (j=0; j<=9; j=j+1) begin + if (a[j] == 1'b1) begin + k_temp = j; end - b_temp [22:0] <= ( (a [9:0] << (k_temp+1'b1)) & 10'h3FF ) << 13; - b_temp [30:23] <= 7'd127 - 4'd15 - k_temp; - b_temp [31] <= a[15]; - end else if (a[14 : 10] == 5'b11111) begin //Infinity/ NAN - b_temp [22:0] <= a [9:0] << 13; - b_temp [30:23] <= 8'hFF; - b_temp [31] <= a[15]; - end else begin //Normalized Number - b_temp [22:0] <= a [9:0] << 13; - b_temp [30:23] <= 7'd127 - 4'd15 + a[14:10]; - b_temp [31] <= a[15]; end + k = 9 - k_temp; + + b_temp [22:0] = ( (a [9:0] << (k+1'b1)) & 10'h3FF ) << 13; + b_temp [30:23] = 7'd127 - 4'd15 - k; + b_temp [31] = a[15]; + end + + else if ( a[14 : 10] == 5'b11111 ) begin //Infinity/ NAN + b_temp [22:0] = a [9:0] << 13; + b_temp [30:23] = 8'hFF; + b_temp [31] = a[15]; + end + + else begin //Normalized Number + b_temp [22:0] = a [9:0] << 13; + b_temp [30:23] = 7'd127 - 4'd15 + a[14:10]; + b_temp [31] = a[15]; end end +end assign b = b_temp; @@ -16895,13 +16881,13 @@ module FPAddSub_a_systolic_4x4_fp( always @(*) begin // Rotate {0 | 4 | 8 | 12} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl2 <= Stage1[23:0]; + 2'b00: Lvl2 <= Stage1[23:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[27:4]; + 2'b01: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end Lvl2[23:19] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[31:8]; + 2'b10: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end Lvl2[23:15] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[35:12]; + 2'b11: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[23:11] <= 0; end endcase end @@ -16923,13 +16909,13 @@ module FPAddSub_a_systolic_4x4_fp( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_2[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[23:0]; + 2'b00: Lvl3 <= Stage2[23:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[24:1]; + 2'b01: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end Lvl3[23] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[25:2]; + 2'b10: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end Lvl3[23:22] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[26:3]; + 2'b11: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end Lvl3[23:21] <= 0; end endcase end @@ -17068,11 +17054,11 @@ module FPAddSub_c_systolic_4x4_fp( // Rotate by 0 2'b00: Lvl2 <= Stage1[32:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[61:29]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[57:25]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[53:21]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -17081,13 +17067,13 @@ module FPAddSub_c_systolic_4x4_fp( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[32:0]; + 2'b00: Lvl3 <= Stage2[32:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[64:32]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[63:31]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[62:30]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -18059,6 +18045,9 @@ module FPAddSub_AlignShift1( wire [2*`MANTISSA+1:0] Stage1; integer i; // Loop variable + wire [`MANTISSA:0] temp_0; + +assign temp_0 = 0; always @(*) begin if (bf16 == 1'b1) begin @@ -18066,36 +18055,36 @@ module FPAddSub_AlignShift1( //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width - Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 'd0 : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width end else begin //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. - Lvl1 <= Shift[2] ? 'd0 : {1'b1, MminP}; + Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP}; end end - assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + assign Stage1 = { Lvl1, Lvl1}; //2*MANTISSA + 2 width always @(*) begin // Rotate {0 | 4 } bits if(bf16 == 1'b1) begin case (Shift[0]) // Rotate by 0 - 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; // Rotate by 4 - 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + 1'b1: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end endcase end else begin case (Shift[1:0]) // Rotate {0 | 4 | 8} bits // Rotate by 0 - 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + 2'b01: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + 2'b10: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end end // Rotate by 12 2'b11: Lvl2[`MANTISSA: 0] <= 0; - //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end end endcase end end @@ -18128,18 +18117,18 @@ module FPAddSub_AlignShift2( wire [2*`MANTISSA+1:0] Stage2; integer j; // Loop variable - assign Stage2 = {11'b0, MminP}; + assign Stage2 = {MminP, MminP}; always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + 2'b01: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + 2'b10: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + 2'b11: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end end endcase end @@ -18285,11 +18274,11 @@ module FPAddSub_NormalizeShift1( // Rotate by 0 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[28:13]; + 2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[24:9]; + 2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[20:5]; + 2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -18298,13 +18287,13 @@ module FPAddSub_NormalizeShift1( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[31:16]; + 2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[30:15]; + 2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[29:14]; + 2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -18550,4 +18539,3 @@ end end endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.4.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.4.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.4.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.4.v index 4a3e3935e30..1ff645073b4 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.4.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.4.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [543:0] top_inp, output [1845:0] top_outp); @@ -21300,7 +21293,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -22130,13 +22123,13 @@ module FPAddSub_a_dspchain( always @(*) begin // Rotate {0 | 4 | 8 | 12} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl2 <= Stage1[23:0]; + 2'b00: Lvl2 <= Stage1[23:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[27:4]; + 2'b01: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end Lvl2[23:19] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[31:8]; + 2'b10: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end Lvl2[23:15] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[35:12]; + 2'b11: begin for (i=0; i<=23; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[23:11] <= 0; end endcase end @@ -22158,13 +22151,13 @@ module FPAddSub_a_dspchain( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_2[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[23:0]; + 2'b00: Lvl3 <= Stage2[23:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[24:1]; + 2'b01: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end Lvl3[23] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[25:2]; + 2'b10: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end Lvl3[23:22] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[26:3]; + 2'b11: begin for (j=0; j<=23; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end Lvl3[23:21] <= 0; end endcase end @@ -22303,11 +22296,11 @@ module FPAddSub_c_dspchain( // Rotate by 0 2'b00: Lvl2 <= Stage1[32:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[61:29]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[57:25]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[53:21]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -22316,13 +22309,13 @@ module FPAddSub_c_dspchain( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[32:0]; + 2'b00: Lvl3 <= Stage2[32:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[64:32]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[63:31]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[62:30]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -22666,7 +22659,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -22880,7 +22873,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -23104,7 +23097,7 @@ begin address = 5'd2; else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd3; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd4; end 4'b0001:begin @@ -23126,7 +23119,7 @@ begin address = 5'd12; else if((x_comp[11:0] >= 16'hccd) && (x_comp[11:0] < 16'he66)) address = 5'd13; - else + else if(x_comp[11:0] >= 16'he66) address = 5'd14; end 4'b0010:begin @@ -23142,7 +23135,7 @@ begin address = 5'd19; else if((x_comp[11:0] >= 16'h800) && (x_comp[11:0] < 16'h99a)) address = 5'd20; - else + else if(x_comp[11:0] >= 16'h99a) address = 5'd21; end default: address = 0; @@ -23259,7 +23252,7 @@ begin begin address = 6'd11; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd12; end @@ -23279,7 +23272,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -23299,7 +23292,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -23319,7 +23312,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -23339,7 +23332,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -23359,7 +23352,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -23379,7 +23372,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -24267,42 +24260,46 @@ module FPAddSub_AlignShift1( wire [2*`MANTISSA+1:0] Stage1; integer i; // Loop variable + wire [`MANTISSA:0] temp_0; + +assign temp_0 = 0; + always @(*) begin if (bf16 == 1'b1) begin //hardcoding for bfloat16 //For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7. //Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits. //Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width - Lvl1 <= (|Shift[`EXPONENT-3:1]) ? 'd0 : {1'b1, MminP}; // MANTISSA + 1 width + Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width end else begin //for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made. - Lvl1 <= Shift[2] ? 'd0 : {1'b1, MminP}; + Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP}; end end - assign Stage1 = {Lvl1, Lvl1}; //2*MANTISSA + 2 width + assign Stage1 = { Lvl1, Lvl1}; //2*MANTISSA + 2 width always @(*) begin // Rotate {0 | 4 } bits if(bf16 == 1'b1) begin case (Shift[0]) // Rotate by 0 - 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; + 1'b0: Lvl2 <= Stage1[`MANTISSA:0]; // Rotate by 4 - 1'b1: Lvl2 <= Stage1[`MANTISSA+4:4]; + 1'b1: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end endcase end else begin case (Shift[1:0]) // Rotate {0 | 4 | 8} bits // Rotate by 0 - 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; + 2'b00: Lvl2 <= Stage1[`MANTISSA:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[`MANTISSA+4:4]; + 2'b01: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+4]; end end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[`MANTISSA+8:8]; + 2'b10: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+8]; end end // Rotate by 12 2'b11: Lvl2[`MANTISSA: 0] <= 0; - //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end + //2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end end endcase end end @@ -24340,13 +24337,13 @@ module FPAddSub_AlignShift2( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; + 2'b00: Lvl3 <= Stage2[`MANTISSA:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[`MANTISSA+1:1]; + 2'b01: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+1]; end end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[`MANTISSA+2:2]; + 2'b10: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+2]; end end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[`MANTISSA+3:3]; + 2'b11: begin for (j=0; j<=`MANTISSA; j=j+1) begin Lvl3[j] <= Stage2[j+3]; end end endcase end @@ -24492,11 +24489,11 @@ module FPAddSub_NormalizeShift1( // Rotate by 0 2'b00: Lvl2 <= Stage1[`DWIDTH:0]; // Rotate by 4 - 2'b01: Lvl2 <= Stage1[28:13]; + 2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[24:9]; + 2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[20:5]; + 2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl2[i-`DWIDTH -1] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -24505,13 +24502,13 @@ module FPAddSub_NormalizeShift1( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; + 2'b00: Lvl3 <= Stage2[`DWIDTH:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[31:16]; + 2'b01: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[30:15]; + 2'b10: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[29:14]; + 2'b11: begin for (i=33; i>=17; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -24707,4 +24704,3 @@ module FPAddSub_ExceptionModule( assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact} ; endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.5.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.5.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.5.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.5.v index caaade9adb8..2dae595663e 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.5.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.5.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [462:0] top_inp, output [319:0] top_outp); @@ -3821,7 +3814,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -4036,7 +4029,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -7765,7 +7758,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -7979,7 +7972,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -8431,7 +8424,7 @@ begin begin address = 6'd11; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd12; end @@ -8451,7 +8444,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -8471,7 +8464,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -8491,7 +8484,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -8511,7 +8504,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -8531,7 +8524,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -8551,7 +8544,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -8715,4 +8708,3 @@ end end endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.6.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.6.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.6.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.6.v index eaaaeaaa790..bffcffbcbfd 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.6.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.6.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [602:0] top_inp, output [419:0] top_outp); @@ -6925,9 +6918,9 @@ always@(posedge clk) begin intermediate_reg_0 <= inp; end -//wire [1219:0]intermediate_wire_1; -//assign intermediate_wire_1[1219] = intermediate_reg_0[1220]^intermediate_reg_0[1219] ; -//assign intermediate_wire_1[1218:0] = intermediate_reg_0[1218:0] ; +wire [1219:0]intermediate_wire_1; +assign intermediate_wire_1[1219] = intermediate_reg_0[1220]^intermediate_reg_0[1219] ; +assign intermediate_wire_1[1218:0] = intermediate_reg_0[1218:0] ; wire [609:0]intermediate_reg_1; fsm fsm_inst_1_0(.clk(clk),.reset(reset),.i1(intermediate_reg_0[1219]),.i2(intermediate_reg_0[1218]),.o(intermediate_reg_1[609])); @@ -9032,7 +9025,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -9247,7 +9240,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -10201,7 +10194,7 @@ module fifo_512_60bit (clk, rst, clr, din, we, dout, re, full, empty); -localparam max_size = 1<=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end // Rotate by 8 - 2'b10: Lvl2 <= Stage1[57:25]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end // Rotate by 12 - 2'b11: Lvl2 <= Stage1[53:21]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end endcase end @@ -16044,13 +16030,13 @@ module FPAddSub_c_systolic_4x4_fp( always @(*) begin // Rotate {0 | 1 | 2 | 3} bits case (Shift_1[1:0]) // Rotate by 0 - 2'b00: Lvl3 <= Stage2[32:0]; + 2'b00: Lvl3 <= Stage2[32:0]; // Rotate by 1 - 2'b01: Lvl3 <= Stage2[64:32]; + 2'b01: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-1]; end Lvl3[0] <= 0; end // Rotate by 2 - 2'b10: Lvl3 <= Stage2[63:31]; + 2'b10: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end // Rotate by 3 - 2'b11: Lvl3 <= Stage2[62:30]; + 2'b11: begin for (i=65; i>=33; i=i-1) begin Lvl3[i-33] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end endcase end @@ -16654,7 +16640,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -16868,7 +16854,7 @@ always @(posedge clk) begin activation_in_progress <= 0; in_data_available_flopped <= in_data_available; end else if(in_data_available || activation_in_progress) begin - cycle_count <= cycle_count + 1; + cycle_count = cycle_count + 1; for (i = 0; i < `DESIGN_SIZE; i=i+1) begin if(activation_type==1'b1) begin // tanH @@ -17321,7 +17307,7 @@ begin begin address = 6'd11; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd12; end @@ -17341,7 +17327,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -17361,7 +17347,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -17381,7 +17367,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -17401,7 +17387,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -17421,7 +17407,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -17441,7 +17427,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -17475,4 +17461,3 @@ end endmodule - diff --git a/vtr_flow/benchmarks/verilog/koios/proxy.8.v b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.8.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/proxy.8.v rename to vtr_flow/benchmarks/verilog/koios_proxy/proxy.8.v index 1aede55ad6c..d0c3f19e0bb 100644 --- a/vtr_flow/benchmarks/verilog/koios/proxy.8.v +++ b/vtr_flow/benchmarks/verilog/koios_proxy/proxy.8.v @@ -1,10 +1,3 @@ -////////////////////////////////////////////////////////////////////////////// -// Proxy/Synthetic benchmark generated from: https://github.com/UT-LCA/koios_proxy_benchmarks -////////////////////////////////////////////////////////////////////////////// - -////////////////////////////////////////////////////////////////////////////// -// Author: Karan Mathur (modified by Aman Arora) -////////////////////////////////////////////////////////////////////////////// module top (input clk, input reset,input [343:0] top_inp, output [655:0] top_outp); @@ -5288,7 +5281,7 @@ end always@(posedge clk) begin - next_state <= current_state; + next_state = current_state; case(current_state) 2'b00: begin @@ -5503,7 +5496,7 @@ output [31:0] chainout, result; reg [15:0] top_a_reg,top_b_reg,bot_a_reg,bot_b_reg; reg [31:0] chainin_reg; -reg [31:0] r1,r2,r3; +wire [31:0] r1,r2,r3; always@(posedge clk) begin if(reset) begin top_a_reg<= 16'b0; @@ -6457,7 +6450,7 @@ module fifo_256_40bit (clk, rst, clr, din, we, dout, re, full, empty); -localparam max_size = 1< 12'hccd) begin address = 6'd12; end @@ -10081,7 +10074,7 @@ begin begin address = 6'd16; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd17; end @@ -10101,7 +10094,7 @@ begin begin address = 6'd21; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd22; end @@ -10121,7 +10114,7 @@ begin begin address = 6'd26; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd27; end @@ -10141,7 +10134,7 @@ begin begin address = 6'd31; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd32; end @@ -10161,7 +10154,7 @@ begin begin address = 6'd36; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd37; end @@ -10181,7 +10174,7 @@ begin begin address = 6'd41; end - else + else if(x[11:0] > 12'hccd) begin address = 6'd42; end @@ -10301,4 +10294,3 @@ dual_port_ram u_dual_port_ram( `endif endmodule - diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt index c9831870b57..cd409943dbb 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml aes_cipher.v common 18.53 parmys 449.26 MiB -1 -1 15.62 460044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml aes_inv_cipher.v common 18.57 parmys 456.23 MiB -1 -1 16.18 467176 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml 8051.v common 9.39 parmys 72.02 MiB -1 -1 7.45 73744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml ethmac.v common 10.80 parmys 105.79 MiB -1 -1 8.57 108328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mips_16.v common 2.22 parmys 23.50 MiB -1 -1 0.48 24064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml xtea.v common 2.60 parmys 32.87 MiB -1 -1 0.78 33660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml aes_cipher.v common 18.53 parmys 449.26 MiB -1 -1 15.62 460044 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml aes_inv_cipher.v common 18.57 parmys 456.23 MiB -1 -1 16.18 467176 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml 8051.v common 9.39 parmys 72.02 MiB -1 -1 7.45 73744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml ethmac.v common 10.80 parmys 105.79 MiB -1 -1 8.57 108328 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mips_16.v common 2.22 parmys 23.50 MiB -1 -1 0.48 24064 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml xtea.v common 2.60 parmys 32.87 MiB -1 -1 0.78 33660 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios_medium/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/parmys_reg_basic/koios_medium/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios_medium/config/golden_results.txt similarity index 76% rename from vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/parmys_reg_basic/koios_medium/config/golden_results.txt index 08c9fbcd7f1..fd00e20ded3 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/koios_medium/config/golden_results.txt @@ -1,13 +1,13 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 18.42 parmys 193.73 MiB -1 -1 15.54 198380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 22.44 parmys 241.20 MiB -1 -1 19.26 246984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 69.72 parmys 729.88 MiB -1 -1 64.55 747392 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 60.13 parmys 715.25 MiB -1 -1 55.57 732416 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 30.82 parmys 313.96 MiB -1 -1 28.88 321500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 20.67 parmys 260.07 MiB -1 -1 18.02 266312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 16.96 parmys 147.62 MiB -1 -1 13.04 151160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 5.73 parmys 84.64 MiB -1 -1 5.38 86676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 17.37 parmys 241.69 MiB -1 -1 16.38 247488 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 21.40 parmys 298.70 MiB -1 -1 18.62 305872 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 14.77 parmys 186.96 MiB -1 -1 10.43 191448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 16.97 parmys 289.46 MiB -1 -1 12.38 296404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 18.42 parmys 193.73 MiB -1 -1 15.54 198380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 22.44 parmys 241.20 MiB -1 -1 19.26 246984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 69.72 parmys 729.88 MiB -1 -1 64.55 747392 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 60.13 parmys 715.25 MiB -1 -1 55.57 732416 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 30.82 parmys 313.96 MiB -1 -1 28.88 321500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 20.67 parmys 260.07 MiB -1 -1 18.02 266312 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 16.96 parmys 147.62 MiB -1 -1 13.04 151160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 5.73 parmys 84.64 MiB -1 -1 5.38 86676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 17.37 parmys 241.69 MiB -1 -1 16.38 247488 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 21.40 parmys 298.70 MiB -1 -1 18.62 305872 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 14.77 parmys 186.96 MiB -1 -1 10.43 191448 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 16.97 parmys 289.46 MiB -1 -1 12.38 296404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt index 9812e0e24f5..45137dcd091 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/task_list.txt @@ -1,4 +1,4 @@ -regression_tests/parmys_reg_basic/koios/ +regression_tests/parmys_reg_basic/koios_medium/ regression_tests/parmys_reg_basic/vtr_benchmarks/ regression_tests/parmys_reg_basic/ultraembedded/ regression_tests/parmys_reg_basic/vexriscv/ diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt index 3f32a270af0..f4de0b58ec4 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/ultraembedded/config/golden_results.txt @@ -1,6 +1,6 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml enet_core.v common 3.39 parmys 44.49 MiB -1 -1 1.96 45560 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mmc_core.v common 3.20 parmys 47.88 MiB -1 -1 2.88 49024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml soc_core.v common 4.29 parmys 54.51 MiB -1 -1 3.77 55820 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml uriscv_core.v common 5.90 parmys 59.29 MiB -1 -1 3.89 60708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml usb_uart_core.v common 5.90 parmys 47.80 MiB -1 -1 3.79 48952 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml enet_core.v common 3.39 parmys 44.49 MiB -1 -1 1.96 45560 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mmc_core.v common 3.20 parmys 47.88 MiB -1 -1 2.88 49024 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml soc_core.v common 4.29 parmys 54.51 MiB -1 -1 3.77 55820 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml uriscv_core.v common 5.90 parmys 59.29 MiB -1 -1 3.89 60708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml usb_uart_core.v common 5.90 parmys 47.80 MiB -1 -1 3.79 48952 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt index ea3bc687884..31a6668e2c4 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vexriscv/config/golden_results.txt @@ -1,13 +1,13 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuMaxPerf.v common 7.86 parmys 58.63 MiB -1 -1 5.42 60040 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuNoCache.v common 4.05 parmys 52.39 MiB -1 -1 3.28 53652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmu.v common 7.24 parmys 58.08 MiB -1 -1 5.82 59472 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFull.v common 8.84 parmys 65.60 MiB -1 -1 7.43 67172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalancedSmp.v common 12.34 parmys 82.25 MiB -1 -1 11.02 84220 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalanced.v common 10.81 parmys 78.95 MiB -1 -1 9.63 80848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvNoCacheNoMmuMaxPerf.v common 6.70 parmys 54.23 MiB -1 -1 4.96 55528 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSecure.v common 13.41 parmys 90.82 MiB -1 -1 10.93 93004 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductiveICache.v common 4.27 parmys 39.73 MiB -1 -1 2.03 40684 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductive.v common 4.27 parmys 38.98 MiB -1 -1 2.00 39912 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallestNoCsr.v common 3.76 parmys 34.54 MiB -1 -1 1.53 35372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallest.v common 4.27 parmys 36.97 MiB -1 -1 1.92 37856 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuMaxPerf.v common 7.86 parmys 58.63 MiB -1 -1 5.42 60040 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuNoCache.v common 4.05 parmys 52.39 MiB -1 -1 3.28 53652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmu.v common 7.24 parmys 58.08 MiB -1 -1 5.82 59472 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFull.v common 8.84 parmys 65.60 MiB -1 -1 7.43 67172 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalancedSmp.v common 12.34 parmys 82.25 MiB -1 -1 11.02 84220 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalanced.v common 10.81 parmys 78.95 MiB -1 -1 9.63 80848 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvNoCacheNoMmuMaxPerf.v common 6.70 parmys 54.23 MiB -1 -1 4.96 55528 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSecure.v common 13.41 parmys 90.82 MiB -1 -1 10.93 93004 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductiveICache.v common 4.27 parmys 39.73 MiB -1 -1 2.03 40684 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductive.v common 4.27 parmys 38.98 MiB -1 -1 2.00 39912 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallestNoCsr.v common 3.76 parmys 34.54 MiB -1 -1 1.53 35372 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallest.v common 4.27 parmys 36.97 MiB -1 -1 1.92 37856 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt index e4b1d588da3..a9f86a276ee 100644 --- a/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/parmys_reg_basic/vtr_benchmarks/config/golden_results.txt @@ -1,22 +1,22 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 25.65 parmys 123.91 MiB -1 -1 21.77 126888 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 43.76 parmys 606.86 MiB -1 -1 42.07 621424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 12.44 parmys 247.64 MiB -1 -1 10.97 253584 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 13.76 parmys 49.20 MiB -1 -1 12.89 50380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.39 parmys 24.57 MiB -1 -1 0.42 25160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 1.49 parmys 27.95 MiB -1 -1 0.49 28620 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 1.13 parmys 27.03 MiB -1 -1 0.37 27676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 13.73 parmys 122.91 MiB -1 -1 12.24 125864 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 2.32 parmys 31.36 MiB -1 -1 1.24 32108 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 8.34 parmys 56.53 MiB -1 -1 5.79 57884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 4.75 parmys 66.23 MiB -1 -1 3.94 67824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 3.98 parmys 46.64 MiB -1 -1 3.41 47764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 3.54 parmys 48.05 MiB -1 -1 2.40 49200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 3.97 parmys 37.42 MiB -1 -1 2.78 38320 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 10.26 parmys 103.86 MiB -1 -1 9.13 106348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 7.96 parmys 124.97 MiB -1 -1 7.30 127968 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 12.34 parmys 197.93 MiB -1 -1 10.96 202676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 parmys 27.84 MiB -1 -1 0.57 28504 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 54.25 parmys 445.89 MiB -1 -1 50.87 456592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 127.93 parmys 1.40 GiB -1 -1 123.93 1466764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 153.73 parmys 1.18 GiB -1 -1 150.40 1233652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/dani/CLionProjects/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 25.65 parmys 123.91 MiB -1 -1 21.77 126888 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 43.76 parmys 606.86 MiB -1 -1 42.07 621424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 12.44 parmys 247.64 MiB -1 -1 10.97 253584 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 13.76 parmys 49.20 MiB -1 -1 12.89 50380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.39 parmys 24.57 MiB -1 -1 0.42 25160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 1.49 parmys 27.95 MiB -1 -1 0.49 28620 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 1.13 parmys 27.03 MiB -1 -1 0.37 27676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 13.73 parmys 122.91 MiB -1 -1 12.24 125864 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 2.32 parmys 31.36 MiB -1 -1 1.24 32108 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 8.34 parmys 56.53 MiB -1 -1 5.79 57884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 4.75 parmys 66.23 MiB -1 -1 3.94 67824 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 3.98 parmys 46.64 MiB -1 -1 3.41 47764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 3.54 parmys 48.05 MiB -1 -1 2.40 49200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 3.97 parmys 37.42 MiB -1 -1 2.78 38320 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 10.26 parmys 103.86 MiB -1 -1 9.13 106348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 7.96 parmys 124.97 MiB -1 -1 7.30 127968 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 12.34 parmys 197.93 MiB -1 -1 10.96 202676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.39 parmys 27.84 MiB -1 -1 0.57 28504 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 54.25 parmys 445.89 MiB -1 -1 50.87 456592 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 127.93 parmys 1.40 GiB -1 -1 123.93 1466764 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 153.73 parmys 1.18 GiB -1 -1 150.40 1233652 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 success unknown unknown unknown unknown dev /home/vtr-verilog-to-routing -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_multi_arch/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/config.txt similarity index 93% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/config.txt index 582e7f94a1d..e372ece9fe7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/config.txt @@ -7,7 +7,7 @@ circuits_dir=benchmarks/verilog/koios # Path to directory of architectures to use -archs_dir=arch/timing +archs_dir=arch/COFFE_22nm # Add circuits to list to sweep. # Some of these benchmarks are designs with hard dsp and ram blocks. @@ -27,7 +27,7 @@ circuit_list_add=spmv.v circuit_list_add=softmax.v # Add architectures to list to sweep -arch_list_add=k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml # Parse info and how to parse parse_file=vpr_standard.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt new file mode 100644 index 00000000000..701f8cf0b06 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb/config/golden_results.txt @@ -0,0 +1,13 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 2297.73 vpr 2.39 GiB -1 -1 67.66 248916 5 386.57 -1 -1 139588 -1 -1 1092 355 32 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2505488 355 289 47792 39479 2 22463 2033 136 136 18496 dsp_top auto 315.6 MiB 829.80 417547 2035967 800879 1110613 124475 2446.8 MiB 59.61 0.36 7.56032 -98878.8 -7.56032 2.65337 18.45 0.123782 0.101211 21.3991 17.4955 -1 526122 14 5.92627e+08 1.02128e+08 4.08527e+08 22087.3 15.74 27.6882 23.1868 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 2034.94 vpr 2.43 GiB -1 -1 56.02 302204 5 517.89 -1 -1 139816 -1 -1 1447 357 58 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2549132 357 289 56236 49095 2 21896 2417 136 136 18496 dsp_top auto 393.4 MiB 344.10 429105 2548015 930606 1466225 151184 2489.4 MiB 85.48 0.50 7.79199 -137248 -7.79199 2.69372 18.37 0.163784 0.137256 28.7844 22.9255 -1 558155 17 5.92627e+08 1.15867e+08 4.08527e+08 22087.3 23.93 38.6761 31.6913 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 8355.37 vpr 1.83 GiB -1 -1 172.77 753612 6 2243.64 -1 -1 412976 -1 -1 4119 206 132 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 1920604 206 13 177171 148374 1 74857 4582 88 88 7744 dsp_top auto 1112.1 MiB 5121.00 676743 4607543 1735144 2771118 101281 1657.7 MiB 309.31 2.26 6.5785 -161896 -6.5785 6.5785 6.26 0.492287 0.382534 63.1824 50.6687 -1 975264 23 2.4541e+08 1.61532e+08 1.69370e+08 21871.2 57.11 95.977 78.7754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 1618.20 vpr 2.03 GiB -1 -1 148.99 734288 3 121.88 -1 -1 410764 -1 -1 6192 260 0 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 2131528 260 122 206267 154358 1 87325 6637 87 87 7569 clb auto 1304.8 MiB 399.50 897507 7862107 3019050 4332770 510287 1741.6 MiB 424.98 3.12 6.46586 -141256 -6.46586 6.46586 5.97 0.627132 0.490712 79.1961 63.5977 -1 1180668 18 2.37162e+08 1.8877e+08 1.65965e+08 21927.0 60.49 113.428 92.6149 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1729.79 vpr 1021.84 MiB -1 -1 73.36 310644 5 38.59 -1 -1 134084 -1 -1 1001 1052 194 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 1046360 1052 32 45949 36457 1 23649 2377 82 82 6724 dsp_top auto 318.7 MiB 1157.86 249259 2491926 887441 1477477 127008 1021.8 MiB 80.90 0.50 5.61569 -89457.4 -5.61569 5.61569 4.88 0.191145 0.16383 32.245 26.936 -1 392147 17 2.09174e+08 7.95104e+07 1.47429e+08 21925.8 21.67 42.3022 35.7727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 910.04 vpr 1.37 GiB -1 -1 41.42 284544 9 33.78 -1 -1 59624 -1 -1 1840 1016 21 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 1440816 1016 2244 14898 16146 1 8221 5123 104 104 10816 io auto 158.5 MiB 103.15 67150 6185283 3064252 2304599 816432 1407.0 MiB 69.85 0.70 12.2749 -20922.9 -12.2749 12.2749 10.37 0.179699 0.173811 26.4253 25.3645 -1 96666 16 3.44415e+08 5.47424e+07 2.37404e+08 21949.3 9.29 34.0737 32.7516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 797.24 vpr 832.35 MiB -1 -1 26.76 177964 4 364.55 -1 -1 101792 -1 -1 1098 91 56 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 852324 91 65 43857 37256 2 18510 1394 72 72 5184 dsp_top auto 308.4 MiB 98.64 227041 912122 302493 573520 36109 832.3 MiB 44.67 0.35 7.31814 -86987.7 -7.31814 2.47624 3.57 0.135265 0.111575 16.8608 14.0592 -1 308420 13 1.63139e+08 5.96656e+07 1.13044e+08 21806.4 12.49 23.3365 19.9484 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 558.43 vpr 451.04 MiB -1 -1 47.68 198932 5 54.72 -1 -1 74068 -1 -1 663 151 72 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 461860 151 97 23485 20309 2 11425 989 50 50 2500 memory auto 200.2 MiB 299.25 132763 513189 156241 330542 26406 451.0 MiB 24.02 0.23 3.82213 -21817.1 -3.82213 1.88661 1.35 0.0922014 0.0776952 9.9325 8.44818 -1 198853 18 7.5303e+07 2.99354e+07 5.42358e+07 21694.3 9.82 15.1262 13.1308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 324.68 vpr 476.87 MiB -1 -1 28.39 239872 5 19.83 -1 -1 76752 -1 -1 896 3 84 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 488316 3 384 24554 22922 1 12214 1385 52 52 2704 memory auto 219.6 MiB 40.02 109481 819387 260846 488959 69582 476.9 MiB 46.92 0.42 5.75775 -36502.7 -5.75775 5.75775 1.61 0.119645 0.0954336 13.4392 11.0442 -1 178203 17 8.30642e+07 4.11342e+07 5.85728e+07 21661.5 11.41 19.6539 16.461 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 204.28 vpr 318.96 MiB -1 -1 31.40 293560 6 21.07 -1 -1 73228 -1 -1 673 37 52 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 326612 37 17 16377 14132 1 8880 779 38 38 1444 memory auto 169.7 MiB 37.77 101035 276670 71311 196113 9246 308.4 MiB 22.68 0.30 5.64757 -37754.9 -5.64757 5.64757 0.69 0.121147 0.0966607 8.12139 6.72187 -1 166084 16 4.31434e+07 2.59385e+07 3.09543e+07 21436.5 10.64 12.6708 10.817 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 465.52 vpr 956.71 MiB -1 -1 16.58 185516 6 27.63 -1 -1 68516 -1 -1 653 82 232 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 979676 82 17 16181 14277 1 8919 1016 84 84 7056 memory auto 157.9 MiB 39.03 167542 542146 177997 350835 13314 956.7 MiB 17.99 0.16 4.69582 -39328.8 -4.69582 4.69582 5.37 0.0636843 0.0548429 7.40096 6.12028 -1 224643 14 2.2198e+08 5.82813e+07 1.54484e+08 21894.0 8.34 10.7207 9.11101 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 965.10 parmys 473.11 MiB -1 -1 78.77 484468 10 187.85 -1 -1 101808 -1 -1 1372 402 0 -1 success 9550a0d release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-12T17:44:41 mustang /homes/koios 484468 402 150 35357 32385 1 17489 1932 43 43 1849 clb auto 295.5 MiB 521.20 130341 1240816 422311 763123 55382 419.7 MiB 51.59 0.44 8.15438 -24418.6 -8.15438 8.15438 1.01 0.115072 0.100317 13.4907 11.3367 -1 209381 17 5.60835e+07 4.0315e+07 3.97519e+07 21499.1 11.32 20.5495 17.5472 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/golden_results.txt deleted file mode 100644 index 9553b2f2698..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_no_hard_block/config/golden_results.txt +++ /dev/null @@ -1,13 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml tpu_like.small.os.v common 479.44 vpr 1.38 GiB -1 -1 37.42 260284 4 177.07 -1 -1 149228 -1 -1 1372 355 32 265 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1450680 355 289 47812 39499 2 22925 2313 96 96 9216 mult_36 auto 324.1 MiB 17.01 353540 1416.7 MiB 50.85 0.28 6.82352 -98558.6 -6.82352 6.82352 5.35 0.0707246 0.056827 11.9662 9.58651 -1 427740 13 5.62531e+08 1.96412e+08 1.76662e+08 19169.0 27.01 15.3549 12.6229 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml tpu_like.small.ws.v common 609.38 vpr 1.42 GiB -1 -1 32.68 306224 5 244.85 -1 -1 147544 -1 -1 1502 357 48 266 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1491280 357 289 56271 49130 2 21579 2462 96 96 9216 mult_36 auto 385.2 MiB 45.14 353824 1456.3 MiB 56.03 0.38 8.83378 -144638 -8.83378 8.83378 4.71 0.111005 0.0872381 14.8266 11.7348 -1 448596 17 5.62531e+08 2.1258e+08 1.76662e+08 19169.0 56.61 20.6214 16.8742 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml dla_like.small.v common 1285.05 vpr 1.73 GiB -1 -1 94.56 755824 6 913.51 -1 -1 416168 -1 -1 5039 206 72 112 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1811120 206 13 176327 147530 1 62942 5442 85 85 7225 clb auto 1152.8 MiB 48.92 560965 1672.6 MiB 99.00 0.73 6.879 -167602 -6.879 6.879 2.33 0.106464 0.0885723 15.4299 12.3845 -1 772789 15 4.34884e+08 3.55362e+08 1.37992e+08 19099.2 23.61 23.037 19.218 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bnn.v common 748.77 vpr 2.09 GiB -1 -1 80.99 734172 3 53.87 -1 -1 409292 -1 -1 6605 260 0 63 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2189868 260 122 206342 154433 1 82297 7050 97 97 9409 clb auto 1348.4 MiB 121.45 1019075 2075.3 MiB 254.67 1.25 9.0254 -183968 -9.0254 9.0254 5.79 0.206816 0.181454 41.4562 34.3935 -1 1249020 16 5.71422e+08 3.80897e+08 1.80445e+08 19177.9 22.85 53.2785 44.8324 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml attention_layer.v common 358.98 vpr 951.40 MiB -1 -1 38.21 331176 5 13.18 -1 -1 145368 -1 -1 1107 1052 117 98 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 974236 1052 32 45947 36455 1 23761 2406 76 76 5776 memory auto 310.5 MiB 87.78 226992 951.4 MiB 50.51 0.34 6.32728 -127961 -6.32728 6.32728 2.75 0.0764641 0.0657796 12.9366 10.7991 -1 336358 18 3.49248e+08 1.62582e+08 1.09907e+08 19028.2 62.50 17.4837 14.8415 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml conv_layer_hls.v common 273.54 vpr 1.48 GiB -1 -1 22.06 300496 9 16.26 -1 -1 60672 -1 -1 1841 1016 21 2 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1552860 1016 2244 14879 16127 1 8171 5124 104 104 10816 io auto 145.1 MiB 15.93 67760 1516.5 MiB 30.83 0.36 13.076 -23196.6 -13.076 13.076 5.59 0.0715582 0.0686397 10.0277 9.47244 -1 94726 15 6.67561e+08 1.11522e+08 2.07956e+08 19226.7 5.91 13.1616 12.462 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml conv_layer.v common 328.83 vpr 598.44 MiB -1 -1 15.25 175872 4 176.65 -1 -1 107056 -1 -1 1101 91 56 84 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 612804 91 65 43907 37306 2 18526 1397 56 56 3136 mult_36 auto 296.4 MiB 18.77 192096 598.4 MiB 31.89 0.25 5.24884 -82910 -5.24884 5.24884 1.36 0.0817701 0.0646584 9.56055 7.69838 -1 258151 15 1.8697e+08 1.23291e+08 5.89565e+07 18799.9 28.11 13.699 11.3901 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml eltwise_layer.v common 189.29 vpr 602.07 MiB -1 -1 27.00 199540 5 28.44 -1 -1 78160 -1 -1 756 151 72 6 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 616524 151 97 23447 20271 2 10524 1082 60 60 3600 memory auto 189.0 MiB 16.24 173459 602.1 MiB 16.33 0.14 4.30258 -22760.4 -4.30258 4.30258 1.74 0.0474894 0.0371599 5.39749 4.3488 -1 225766 14 2.12673e+08 8.2577e+07 6.77353e+07 18815.4 34.88 7.8739 6.57755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml robot_rl.v common 125.09 vpr 463.58 MiB -1 -1 16.61 245220 5 10.41 -1 -1 86940 -1 -1 928 3 48 18 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 474708 3 384 25386 23598 1 12374 1381 50 50 2500 memory auto 210.8 MiB 13.88 111473 463.6 MiB 24.42 0.22 6.23564 -44036 -6.23564 6.23564 1.09 0.0494512 0.0433897 6.01442 5.06495 -1 173651 14 1.47946e+08 8.34473e+07 4.69174e+07 18767.0 11.36 8.85679 7.61607 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml reduction_layer.v common 106.94 vpr 362.52 MiB -1 -1 18.22 314720 5 10.07 -1 -1 74224 -1 -1 724 37 32 0 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 371216 37 17 17222 14977 1 9101 810 44 44 1936 memory auto 160.5 MiB 13.46 117165 362.5 MiB 16.31 0.18 6.89003 -43102.8 -6.89003 6.89003 0.86 0.0424464 0.0334215 4.30126 3.45338 -1 178442 17 1.12988e+08 5.65561e+07 3.58735e+07 18529.7 11.90 6.75972 5.65566 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spmv.v common 406.75 vpr 1.59 GiB -1 -1 9.52 196892 6 16.87 -1 -1 70172 -1 -1 660 82 229 32 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1664692 82 17 16147 14243 1 8863 1020 108 108 11664 memory auto 143.6 MiB 11.62 193377 1625.7 MiB 11.91 0.09 7.3348 -55467.8 -7.3348 7.3348 6.95 0.0326617 0.0280682 4.35245 3.56645 -1 236358 13 7.15542e+08 1.7373e+08 2.24153e+08 19217.5 151.91 6.02959 5.06754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml softmax.v common 257.73 yosys 483.48 MiB -1 -1 44.14 495088 10 92.58 -1 -1 103504 -1 -1 1441 402 0 8 success 327aa1d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T16:01:10 gh-actions-runner-vtr-auto-spawned87 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 470996 402 150 35425 32453 1 16902 2001 46 46 2116 clb auto 287.8 MiB 28.32 137413 459.5 MiB 37.09 0.27 8.07166 -26850.7 -8.07166 8.07166 1.16 0.0542866 0.047736 8.12624 6.83714 -1 211731 16 1.23052e+08 8.0831e+07 3.94611e+07 18648.9 6.40 11.8606 10.1861 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt index 0dbb0be653d..79c591dd4e0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/task_list.txt @@ -1,4 +1,4 @@ -regression_tests/vtr_reg_nightly_test4/koios_multi_arch -regression_tests/vtr_reg_nightly_test4/koios -regression_tests/vtr_reg_nightly_test4/koios_no_hard_block +regression_tests/vtr_reg_nightly_test4/koios_medium_multi_arch +regression_tests/vtr_reg_nightly_test4/koios_medium +regression_tests/vtr_reg_nightly_test4/koios_medium_no_hb regression_tests/vtr_reg_nightly_test4/titan_s10_qor diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_multi_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_multi_arch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_multi_arch/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/config.txt similarity index 93% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/config.txt index 69969cf6ac1..b3328827ffb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/config.txt @@ -7,7 +7,7 @@ circuits_dir=benchmarks/verilog/koios # Path to directory of architectures to use -archs_dir=arch/timing +archs_dir=arch/COFFE_22nm # Add circuits to list to sweep. # Some of these benchmarks are designs with hard dsp and ram blocks. @@ -27,7 +27,7 @@ circuit_list_add=spmv.v circuit_list_add=softmax.v # Add architectures to list to sweep -arch_list_add=k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml # Parse info and how to parse parse_file=vpr_standard.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt new file mode 100644 index 00000000000..f041c937487 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb/config/golden_results.txt @@ -0,0 +1,13 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.os.v common 2747.02 vpr 2.41 GiB 18.56 244232 -1 -1 5 813.27 -1 -1 161168 -1 -1 1180 355 32 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 2522108 355 289 49464 41111 2 23462 2132 136 136 18496 dsp_top auto 337.4 MiB 858.40 426609 1977236 753155 1108979 115102 2463.0 MiB 58.86 0.43 6.72662 -102588 -6.72662 2.82315 18.26 0.13711 0.109532 20.9749 16.8857 -1 539186 16 5.92627e+08 1.07375e+08 4.08527e+08 22087.3 16.33 28.3747 23.4039 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.ws.v common 2232.36 vpr 2.39 GiB 45.77 310756 -1 -1 6 815.72 -1 -1 133016 -1 -1 1335 357 58 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 2502320 357 289 42535 35250 2 20692 2316 136 136 18496 dsp_top auto 318.6 MiB 211.40 272555 2453036 886091 1358194 208751 2443.7 MiB 67.95 0.41 8.05926 -86680.8 -8.05926 3.09017 18.54 0.148412 0.12937 24.6878 20.6502 -1 369604 15 5.92627e+08 1.15533e+08 4.08527e+08 22087.3 16.59 32.0694 27.2887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 7929.88 vpr 2.21 GiB 111.28 695260 -1 -1 5 4283.70 -1 -1 613948 -1 -1 5610 206 120 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 2312616 206 13 227613 180877 1 95621 6077 90 90 8100 dsp_top auto 1427.2 MiB 2488.60 734239 7045941 2665194 4095981 284766 1914.6 MiB 454.55 3.17 7.91176 -153731 -7.91176 7.91176 6.87 0.585963 0.502656 84.3646 69.5641 -1 1028712 20 2.56465e+08 2.05545e+08 1.77260e+08 21883.9 54.73 120.33 100.532 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 2156.94 vpr 2.14 GiB 49.84 497956 -1 -1 3 318.58 -1 -1 498800 -1 -1 5692 260 0 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 2246412 260 122 231647 179602 1 86408 6137 83 83 6889 clb auto 1449.4 MiB 638.69 893333 6577208 2542738 3721436 313034 1764.5 MiB 470.57 3.15 6.59918 -139825 -6.59918 6.59918 5.83 0.687477 0.581414 91.1484 74.1515 -1 1169713 17 2.13666e+08 1.74818e+08 1.51189e+08 21946.4 57.80 126.618 104.568 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 2645.61 vpr 1.34 GiB 23.15 622648 -1 -1 8 163.18 -1 -1 298492 -1 -1 1594 1048 194 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 1407616 1048 32 64005 53342 1 37273 3004 94 94 8836 dsp_top auto 467.1 MiB 1843.78 328521 3621226 1320758 2080480 219988 1374.6 MiB 111.17 0.67 7.0562 -103278 -7.0562 7.0562 7.55 0.222052 0.191606 39.6453 33.3594 -1 491200 18 2.78391e+08 1.05701e+08 1.93746e+08 21926.9 22.20 51.7744 43.9716 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 1420.50 odin 3.93 GiB 126.64 4122864 -1 -1 7 109.07 -1 -1 1643132 -1 -1 1885 1016 21 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 1505544 1016 2283 16425 17373 1 9337 5207 106 106 11236 io auto 175.5 MiB 162.67 74004 6365999 3190044 2346352 829603 1470.3 MiB 65.01 0.67 10.6615 -20482.8 -10.6615 10.6615 10.97 0.169272 0.163067 24.7953 23.7122 -1 107353 16 3.5748e+08 5.59981e+07 2.46822e+08 21967.1 8.94 31.9124 30.5934 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 1384.92 vpr 878.84 MiB 21.36 229292 -1 -1 4 789.79 -1 -1 138984 -1 -1 1377 91 56 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 899936 91 65 51897 44206 2 22476 1673 72 72 5184 dsp_top auto 376.6 MiB 175.09 238390 1173059 390660 732055 50344 878.8 MiB 59.60 0.50 5.37002 -87486.1 -5.37002 3.02646 3.55 0.180223 0.155866 22.218 18.6538 -1 333847 18 1.63139e+08 6.74509e+07 1.13044e+08 21806.4 18.77 31.8066 27.1378 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml eltwise_layer.v common 1772.13 vpr 580.10 MiB 67.69 354176 -1 -1 5 587.29 -1 -1 127416 -1 -1 1459 152 72 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 594020 152 97 41796 36054 2 19915 1786 50 50 2500 memory auto 336.8 MiB 851.60 186239 1669760 524773 1020263 124724 531.3 MiB 70.76 0.45 4.53632 -30837.9 -4.53632 2.86597 1.47 0.169181 0.142039 27.2009 23.3094 -1 274157 15 7.5303e+07 5.21471e+07 5.42358e+07 21694.3 12.88 34.478 29.8525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml robot_rl.v common 1923.57 vpr 541.93 MiB 968.51 369200 -1 -1 6 136.74 -1 -1 162888 -1 -1 1311 3 96 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 554940 3 384 32137 30217 1 16381 1812 52 52 2704 memory auto 294.8 MiB 582.60 149209 1205390 393912 723274 88204 529.2 MiB 56.53 0.52 5.74546 -48383.3 -5.74546 5.74546 1.46 0.154201 0.125988 15.924 13.4294 -1 239540 19 8.30642e+07 5.43664e+07 5.85728e+07 21661.5 13.89 23.8898 20.4955 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml reduction_layer.v common 233.33 vpr 361.37 MiB 4.20 89248 -1 -1 6 58.46 -1 -1 79628 -1 -1 921 37 52 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 370040 37 17 22150 19905 1 11758 1027 38 38 1444 memory auto 212.7 MiB 42.47 126590 420526 110476 301834 8216 324.8 MiB 33.31 0.37 5.55795 -41130.3 -5.55795 5.55795 0.73 0.11313 0.0884186 9.58547 7.89044 -1 196496 15 4.31434e+07 3.28587e+07 3.09543e+07 21436.5 11.19 14.9467 12.6304 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml spmv.v common 1412.08 vpr 950.03 MiB 26.03 719388 -1 -1 6 119.31 -1 -1 264268 -1 -1 789 61 198 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 972832 61 17 22163 20259 1 13092 1097 82 82 6724 memory auto 203.9 MiB 836.89 182828 719282 226786 457521 34975 950.0 MiB 25.55 0.20 4.48792 -36503.8 -4.48792 4.48792 4.82 0.0811124 0.0649828 10.9111 9.15332 -1 236945 16 2.09174e+08 5.73955e+07 1.47429e+08 21925.8 9.64 15.2365 13.034 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml softmax.v common 1069.10 vpr 516.09 MiB 22.19 331772 -1 -1 10 298.39 -1 -1 111816 -1 -1 1450 402 0 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 528476 402 150 39533 35581 1 18187 2010 44 44 1936 clb auto 325.6 MiB 573.81 131926 1308050 432849 828619 46582 452.6 MiB 50.04 0.43 7.80443 -23537.6 -7.80443 7.80443 0.99 0.116128 0.101568 13.8532 11.602 -1 214227 15 5.86452e+07 4.24916e+07 4.16874e+07 21532.7 10.21 20.577 17.7298 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/golden_results.txt deleted file mode 100644 index 6bf43ab8797..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block/config/golden_results.txt +++ /dev/null @@ -1,13 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml tpu_like.small.os.v common 761.54 vpr 1.40 GiB 8.94 246548 -1 -1 5 536.08 -1 -1 166152 -1 -1 1444 355 32 276 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 1470756 355 289 49483 41130 2 23896 2396 96 96 9216 mult_36 auto 349.9 MiB 15.14 338433 1436.3 MiB 33.55 0.21 7.32578 -112186 -7.32578 5.34411 3.92 0.0713188 0.0583504 10.1174 8.27355 -1 418388 14 5.62531e+08 2.04648e+08 1.76662e+08 19169.0 17.09 13.533 11.3326 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml tpu_like.small.ws.v common 649.92 vpr 1.43 GiB 24.65 314976 -1 -1 7 370.35 -1 -1 138844 -1 -1 1414 357 48 277 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 1497604 357 289 42501 35216 2 20505 2385 98 98 9604 mult_36 auto 308.8 MiB 18.73 230487 1462.5 MiB 37.10 0.21 8.88998 -94512.7 -8.88998 4.09081 4.54 0.0676504 0.0602512 12.5552 10.3844 -1 301014 15 5.9175e+08 2.12194e+08 1.84766e+08 19238.4 17.32 16.0913 13.5538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml dla_like.small.v common 2453.66 vpr 2.21 GiB 27.04 696596 -1 -1 5 1933.05 -1 -1 615728 -1 -1 6249 206 120 128 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 2312596 206 13 227622 180886 1 84573 6716 94 94 8836 clb auto 1503.0 MiB 80.64 654088 2112.6 MiB 198.65 1.39 9.11963 -180639 -9.11963 9.11963 4.13 0.252917 0.223063 35.4441 29.7289 -1 883338 15 5.40921e+08 4.53209e+08 1.69673e+08 19202.5 43.79 49.2097 41.9441 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bnn.v common 956.14 vpr 2.21 GiB 26.04 523872 -1 -1 3 209.38 -1 -1 499128 -1 -1 6120 260 0 63 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 2315188 260 122 231646 179601 1 81455 6565 93 93 8649 clb auto 1508.8 MiB 211.12 949456 2068.0 MiB 237.83 1.58 8.44927 -182004 -8.44927 8.44927 4.34 0.364939 0.292847 47.7608 38.653 -1 1178443 20 5.27943e+08 3.54761e+08 1.65793e+08 19169.0 38.20 67.7328 55.9057 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml attention_layer.v common 599.50 vpr 1.20 GiB 10.66 629020 -1 -1 7 117.45 -1 -1 302316 -1 -1 1896 1048 134 136 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 1262728 1048 32 63944 53281 1 37450 3246 84 84 7056 memory auto 476.8 MiB 140.66 309717 1233.1 MiB 100.02 0.42 7.31797 -145014 -7.31797 7.31797 4.38 0.120705 0.0990744 25.5356 20.9197 -1 437446 16 4.27124e+08 2.29463e+08 1.34653e+08 19083.5 46.16 31.6496 26.3765 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml conv_layer_hls.v common 534.19 odin 3.93 GiB 76.81 4124736 -1 -1 7 75.28 -1 -1 1641780 -1 -1 1899 1016 21 2 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 1622316 1016 2283 16410 17358 1 9146 5221 106 106 11236 io auto 163.6 MiB 18.87 75402 1584.3 MiB 29.98 0.26 11.3549 -23654.8 -11.3549 11.3549 5.54 0.0723554 0.0699545 11.5278 10.9099 -1 105553 17 6.92108e+08 1.14648e+08 2.16447e+08 19263.7 5.12 15.0473 14.2862 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml conv_layer.v common 728.04 vpr 641.90 MiB 9.81 234440 -1 -1 4 565.53 -1 -1 139096 -1 -1 1399 91 56 84 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 657308 91 65 51851 44160 2 22078 1695 56 56 3136 mult_36 auto 365.3 MiB 21.93 217217 641.9 MiB 27.13 0.21 5.48422 -88338.9 -5.48422 4.43217 1.09 0.0767498 0.062203 9.40161 7.76604 -1 292545 14 1.8697e+08 1.39352e+08 5.89565e+07 18799.9 26.39 13.017 11.023 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml eltwise_layer.v common 482.65 vpr 686.54 MiB 17.32 358148 -1 -1 5 302.86 -1 -1 126652 -1 -1 1520 152 72 6 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 703012 152 97 42180 36438 2 18962 1847 60 60 3600 memory auto 338.4 MiB 32.55 223035 686.5 MiB 28.23 0.21 4.80947 -34667.8 -4.80947 4.538 1.32 0.0708018 0.0585034 9.6045 7.98385 -1 295068 16 2.12673e+08 1.23753e+08 6.77353e+07 18815.4 19.99 13.3613 11.3573 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml robot_rl.v common 569.73 vpr 511.79 MiB 364.25 371024 -1 -1 6 77.39 -1 -1 164068 -1 -1 1396 3 48 18 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 524068 3 384 32738 30662 1 16497 1849 50 50 2500 memory auto 285.3 MiB 21.18 147767 511.8 MiB 35.32 0.31 6.49141 -56723.5 -6.49141 6.49141 0.91 0.0639028 0.0574356 8.96405 7.67125 -1 229992 16 1.47946e+08 1.08671e+08 4.69174e+07 18767.0 13.79 14.2937 12.3489 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml reduction_layer.v common 167.07 vpr 382.35 MiB 1.71 94008 -1 -1 6 51.56 -1 -1 76564 -1 -1 922 37 32 0 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 391528 37 17 22150 19905 1 11743 1008 44 44 1936 memory auto 195.3 MiB 13.88 136075 382.4 MiB 38.68 0.34 5.18198 -48036.2 -5.18198 5.18198 1.38 0.0932507 0.0705171 9.26828 7.27156 -1 199924 15 1.12988e+08 6.72275e+07 3.58735e+07 18529.7 17.42 14.1245 11.4717 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spmv.v common 496.17 vpr 1.41 GiB 13.34 722872 -1 -1 6 66.85 -1 -1 265368 -1 -1 847 61 196 32 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 1473376 61 17 22068 20164 1 12227 1153 100 100 10000 memory auto 198.3 MiB 15.53 194129 1438.8 MiB 20.68 0.14 5.34991 -50443 -5.34991 5.34991 6.66 0.0375414 0.0334369 7.92428 6.4514 -1 228002 13 6.13558e+08 1.65725e+08 1.91890e+08 19189.0 135.92 10.0281 8.3047 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml softmax.v common 350.19 vpr 503.39 MiB 7.45 332728 -1 -1 10 198.11 -1 -1 108564 -1 -1 1522 402 0 8 success v8.0.0-6793-gb52911b9f release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-167-generic x86_64 2022-11-27T15:52:14 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/pack_refactor/vtr-verilog-to-routing 515472 402 150 39517 35566 1 17500 2082 47 47 2209 clb auto 320.7 MiB 28.65 132512 494.5 MiB 46.33 0.43 7.89937 -26203.4 -7.89937 7.89937 0.77 0.123148 0.110184 11.0221 9.4339 -1 207800 16 1.27256e+08 8.51966e+07 4.12548e+07 18675.8 9.98 17.0281 14.6962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/task_list.txt index 2fec61ee358..3a33d371a62 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4_odin/task_list.txt @@ -1,3 +1,3 @@ -regression_tests/vtr_reg_nightly_test4_odin/koios_multi_arch -regression_tests/vtr_reg_nightly_test4_odin/koios -regression_tests/vtr_reg_nightly_test4_odin/koios_no_hard_block +regression_tests/vtr_reg_nightly_test4_odin/koios_medium_multi_arch +regression_tests/vtr_reg_nightly_test4_odin/koios_medium +regression_tests/vtr_reg_nightly_test4_odin/koios_medium_no_hb diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt similarity index 92% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt index 5ad49ccd76b..5c1b1d03abb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/config.txt @@ -18,10 +18,6 @@ circuit_list_add=bwave_like.float.small.v #circuit_list_add=bwave_like.fixed.large.v circuit_list_add=dnnweaver.v circuit_list_add=tdarknet_like.small.v -circuit_list_add=proxy.5.v -#circuit_list_add=proxy.6.v -circuit_list_add=proxy.7.v -circuit_list_add=proxy.8.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt similarity index 63% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt index ab392f278c7..f3dfc0ea25e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other/config/golden_results.txt @@ -2,6 +2,3 @@ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1260.60 vpr 1.65 GiB -1 -1 82.85 943096 6 503.07 -1 -1 203916 -1 -1 1992 114 356 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1727512 114 86 73955 63740 1 36598 2692 104 104 10816 memory auto 602.4 MiB 46.60 824826 1687.0 MiB 116.85 0.90 6.47196 -303223 -6.47196 6.47196 6.03 0.257057 0.204075 33.4945 27.1837 -1 1108103 18 3.44415e+08 1.41138e+08 2.37404e+08 21949.3 76.27 47.2537 39.0222 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 2995.62 vpr 5.21 GiB -1 -1 121.94 1217796 9 1000.94 -1 -1 571064 -1 -1 5866 1428 1144 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5466852 1428 2108 167028 128685 1 100323 10834 194 194 37636 memory auto 1291.1 MiB 278.74 2092925 5338.7 MiB 406.01 2.56 9.34336 -1.35131e+06 -9.34336 9.34336 14.57 0.330195 0.266824 59.6404 49.5844 -1 2887552 17 1.20484e+09 3.94261e+08 8.28785e+08 22021.1 103.20 78.0666 66.033 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 11822.63 vpr 33.73 GiB -1 -1 301.82 1498692 4 2262.81 -1 -1 565160 -1 -1 4071 21 9017 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 35366520 21 26 134015 127194 1 74552 13240 534 534 285156 memory auto 1575.7 MiB 1255.79 3658361 34537.6 MiB 338.82 2.62 14.3492 -1.78071e+06 -14.3492 14.3492 219.35 0.387252 0.315621 66.8828 52.1825 -1 4244397 13 9.28675e+09 1.38166e+09 6.26248e+09 21961.6 73.80 83.5895 66.8884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.5.v common 3363.20 vpr 2.68 GiB -1 -1 154.26 1165368 6 1603.68 -1 -1 301268 -1 -1 3223 465 211 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2810008 465 320 129485 107990 1 58059 4497 136 136 18496 dsp_top auto 841.1 MiB 1082.93 879864 2744.1 MiB 96.27 0.70 8.00822 -243261 -8.00822 8.00822 6.19 0.108058 0.0918654 16.0953 13.2709 -1 1189471 22 5.92627e+08 1.89533e+08 4.08527e+08 22087.3 21.06 24.541 20.8119 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.7.v common 6149.59 vpr 3.11 GiB -1 -1 327.79 3213900 6 2311.60 -1 -1 558028 -1 -1 4947 354 492 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 3261956 354 144 205726 176518 1 87849 6240 138 138 19044 dsp_top auto 1400.6 MiB 2811.30 1566104 3185.5 MiB 189.27 1.35 7.35158 -380661 -7.35158 7.35158 6.76 0.192658 0.162424 28.3852 23.4909 -1 2031848 20 6.09712e+08 2.82667e+08 4.20597e+08 22085.5 44.22 43.0139 36.7238 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.8.v common 3822.98 vpr 3.23 GiB -1 -1 335.67 1596044 6 1851.82 -1 -1 358648 -1 -1 3061 346 236 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 3384032 346 656 128410 107865 1 57492 4667 152 152 23104 dsp_top auto 867.5 MiB 995.48 894414 3304.7 MiB 100.23 0.67 7.67074 -213812 -7.67074 7.67074 8.09 0.126508 0.109839 20.5739 17.3782 -1 1212653 20 7.41832e+08 2.11293e+08 5.09338e+08 22045.4 21.04 29.6792 25.6077 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_multi_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_multi_arch/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_multi_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_multi_arch/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/config.txt similarity index 91% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/config.txt index 7d227214802..b2be608661a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/config.txt @@ -18,10 +18,6 @@ circuit_list_add=bwave_like.float.small.v #circuit_list_add=bwave_like.fixed.large.v circuit_list_add=dnnweaver.v circuit_list_add=tdarknet_like.small.v -circuit_list_add=proxy.5.v -#circuit_list_add=proxy.6.v -circuit_list_add=proxy.7.v -circuit_list_add=proxy.8.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt similarity index 63% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt index d2bca15777b..4f8ca9d3650 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_no_hard_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/koios_other_no_hb/config/golden_results.txt @@ -2,6 +2,3 @@ k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.small.v common 1704.77 vpr 1.73 GiB -1 -1 112.77 1072684 6 972.07 -1 -1 262296 -1 -1 2657 114 356 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1816404 114 86 102099 83868 1 49376 3345 104 104 10816 memory auto 743.0 MiB 66.63 1002333 1773.8 MiB 96.38 0.67 9.71996 -305575 -9.71996 9.71996 3.30 0.156333 0.132423 21.1584 17.4182 -1 1349918 17 3.44415e+08 1.56649e+08 2.37404e+08 21949.3 52.29 30.1635 25.3878 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dnnweaver.v common 3222.53 vpr 5.21 GiB -1 -1 123.94 1231884 9 1003.75 -1 -1 571344 -1 -1 5865 1428 1144 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 5466508 1428 2108 167060 128717 1 100354 10833 194 194 37636 memory auto 1290.9 MiB 282.28 1923492 5338.4 MiB 563.19 2.55 11.8807 -1.40186e+06 -11.8807 11.8807 23.26 0.324762 0.263642 82.6055 68.1074 -1 2737596 16 1.20484e+09 3.94233e+08 8.28785e+08 22021.1 77.10 98.7411 82.5923 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 12022.07 vpr 33.80 GiB -1 -1 375.15 1825460 9 2733.36 -1 -1 600716 -1 -1 4834 21 9017 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 35446888 21 26 151757 142444 1 82530 13915 534 534 285156 memory auto 1706.7 MiB 813.36 3582618 34616.1 MiB 391.34 2.29 18.4106 -1.77608e+06 -18.4106 18.4106 224.47 0.400339 0.326802 71.8404 56.0172 -1 4166999 13 9.28675e+09 1.38061e+09 6.26248e+09 21961.6 73.28 89.659 71.729 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.5.v common 3375.82 vpr 2.68 GiB -1 -1 157.05 1181224 6 1670.64 -1 -1 302764 -1 -1 3191 465 211 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2809460 465 320 129504 108009 1 58473 4465 136 136 18496 dsp_top auto 841.1 MiB 1032.91 884172 2743.6 MiB 95.74 0.66 7.61466 -238962 -7.61466 7.61466 6.14 0.109769 0.0933461 16.6759 13.7585 -1 1191403 17 5.92627e+08 1.8864e+08 4.08527e+08 22087.3 19.73 24.0107 20.3609 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.7.v common 10196.14 yosys 4.67 GiB -1 -1 642.13 4896016 7 5614.10 -1 -1 936724 -1 -1 12162 354 492 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 4769844 354 144 379926 334302 1 166920 13455 138 138 19044 dsp_top auto 2715.2 MiB 2762.96 2262985 4038.2 MiB 597.61 4.40 9.23314 -568660 -9.23314 9.23314 6.90 0.427226 0.37121 57.1942 48.3964 -1 3133698 20 6.09712e+08 4.83995e+08 4.20597e+08 22085.5 83.53 87.8683 75.9098 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 - k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.8.v common 3980.65 vpr 3.60 GiB -1 -1 357.65 1679888 7 2143.92 -1 -1 441900 -1 -1 4133 346 236 -1 success aff6cf6-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-01-23T14:19:07 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 3776448 346 656 177742 145719 1 82353 5755 158 158 24964 dsp_top auto 1124.8 MiB 758.53 1160936 3687.9 MiB 134.07 0.92 8.99891 -298222 -8.99891 8.99891 9.15 0.145764 0.125052 23.0589 19.1926 -1 1569740 17 7.98363e+08 2.45267e+08 5.50593e+08 22055.5 24.82 32.8605 28.0488 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/task_list.txt index 1107b6045f7..b8d7df6f2a9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test6/task_list.txt @@ -1,3 +1,3 @@ -regression_tests/vtr_reg_nightly_test6/koios_multi_arch -regression_tests/vtr_reg_nightly_test6/koios -regression_tests/vtr_reg_nightly_test6/koios_no_hard_block +regression_tests/vtr_reg_nightly_test6/koios_other_multi_arch +regression_tests/vtr_reg_nightly_test6/koios_other +regression_tests/vtr_reg_nightly_test6/koios_other_no_hb diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios_medium/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios_medium/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios_medium/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_parmys/koios_medium/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/task_list.txt index cd8ca106efe..d5d992cf649 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/task_list.txt @@ -1,4 +1,4 @@ -regression_tests/vtr_reg_parmys/koios/ +regression_tests/vtr_reg_parmys/koios_medium/ regression_tests/vtr_reg_parmys/vtr_benchmarks/ regression_tests/vtr_reg_parmys/ultraembedded/ regression_tests/vtr_reg_parmys/vexriscv/ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_no_complex_dsp/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/koios_test_no_hb/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 0576785ed9a..c159711565f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -78,8 +78,8 @@ regression_tests/vtr_reg_strong/strong_unroute_analysis regression_tests/vtr_reg_strong/strong_verify_rr_graph regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin regression_tests/vtr_reg_strong/strong_verify_rr_graph_titan -regression_tests/vtr_reg_strong/koios -regression_tests/vtr_reg_strong/koios_no_complex_dsp +regression_tests/vtr_reg_strong/koios_test +regression_tests/vtr_reg_strong/koios_test_no_hb regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_noc diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_no_complex_dsp/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_no_complex_dsp/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_no_complex_dsp/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_no_complex_dsp/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/koios_test_no_hb/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt index f163b140225..ab44aee0cf4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt @@ -77,7 +77,7 @@ regression_tests/vtr_reg_strong_odin/strong_unroute_analysis regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_bin regression_tests/vtr_reg_strong_odin/strong_verify_rr_graph_titan -regression_tests/vtr_reg_strong_odin/koios -regression_tests/vtr_reg_strong_odin/koios_no_complex_dsp +regression_tests/vtr_reg_strong_odin/koios_test +regression_tests/vtr_reg_strong_odin/koios_test_no_hb regression_tests/vtr_reg_strong_odin/strong_timing_fail regression_tests/vtr_reg_strong_odin/strong_timing_no_fail diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt new file mode 100644 index 00000000000..95b8603ec5b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/config.txt @@ -0,0 +1,38 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=bwave_like.float.large.v + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Add include files to the list. +# Some benchmarks instantiate hard dsp and memory blocks +# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. +# The hard_block_include.v file +# defines this macros, thereby enabling instantiations of the hard blocks +include_list_add=hard_block_include.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 --target_utilization 0.28 \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt new file mode 100644 index 00000000000..84dbd1faeed --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_bwave_float_large/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bwave_like.float.large.v common 165618.16 vpr 6.59 GiB -1 -1 651.44 3507024 6 12185.69 -1 -1 710136 -1 -1 7199 561 1182 -1 exited with return code 2 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6906252 561 532 273542 235554 1 136273 10114 210 210 44100 -1 auto 2151.6 MiB 447.20 4953031 15644018 6777393 8155095 711530 6744.4 MiB 1152.98 7.06 9.98627 -1.64004e+06 -9.98627 9.98627 56.31 1.61599 1.38524 251.774 206.355 -1 -1 -1 -1 -1 -1 -1 148539.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/config.txt new file mode 100644 index 00000000000..b263ad273a6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/config.txt @@ -0,0 +1,38 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=dla_like.large.v + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Add include files to the list. +# Some benchmarks instantiate hard dsp and memory blocks +# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. +# The hard_block_include.v file +# defines this macros, thereby enabling instantiations of the hard blocks +include_list_add=hard_block_include.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 --target_utilization 0.35 \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/golden_results.txt new file mode 100644 index 00000000000..32838c49df2 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_dla_large/config/golden_results.txt @@ -0,0 +1,2 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.large.v common 140378.44 vpr 15.02 GiB -1 -1 982.60 4000316 6 86065.22 -1 -1 2454420 -1 -1 25041 818 864 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 15748860 818 49 1107469 967430 1 437816 28084 303 303 91809 -1 auto 6835.9 MiB 20442.21 8916694 65309818 27350520 35037816 2921482 15379.7 MiB 9022.47 82.54 6.34439 -1.64144e+06 -6.34439 6.34439 191.56 5.44523 4.47553 896.331 733.427 -1 10336095 15 2.96411e+09 1.15064e+09 2.01693e+09 21968.8 15122.30 1124.17 933.441 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt similarity index 81% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt index b3e4ce9bbad..e4261a2b31f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/config.txt @@ -13,16 +13,7 @@ archs_dir=arch/COFFE_22nm includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep -circuit_list_add=proxy.2.v -circuit_list_add=tdarknet_like.large.v -circuit_list_add=proxy.4.v -circuit_list_add=proxy.1.v -circuit_list_add=bwave_like.float.large.v -circuit_list_add=proxy.3.v circuit_list_add=lenet.v -circuit_list_add=deepfreeze.style1.sv -circuit_list_add=deepfreeze.style2.sv -circuit_list_add=deepfreeze.style3.sv circuit_list_add=clstm_like.small.v circuit_list_add=clstm_like.medium.v circuit_list_add=clstm_like.large.v @@ -33,7 +24,6 @@ circuit_list_add=tpu_like.large.ws.v circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v -circuit_list_add=dla_like.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/golden_results.txt new file mode 100644 index 00000000000..087d3c4438b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large/config/golden_results.txt @@ -0,0 +1,12 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 6320.39 parmys 6.81 GiB -1 -1 2279.37 7141128 8 3659.89 -1 -1 229600 -1 -1 1215 3 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 406996 3 73 29130 23346 1 13644 1292 40 40 1600 clb auto 246.6 MiB 64.06 136280 627318 185500 408250 33568 357.7 MiB 81.14 0.66 8.27929 -16089.3 -8.27929 8.27929 1.10 0.16804 0.146992 16.9432 13.6451 -1 224227 19 4.87982e+07 3.41577e+07 3.42310e+07 21394.3 19.75 26.6756 21.8374 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 11605.17 vpr 3.24 GiB -1 -1 669.16 1080564 4 7868.39 -1 -1 606244 -1 -1 7733 652 237 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3400468 652 290 299247 274102 1 72966 9121 120 120 14400 dsp_top auto 1946.1 MiB 741.62 1061263 13535473 5677109 7516142 342222 3001.0 MiB 915.91 6.25 6.0577 -397722 -6.0577 6.0577 16.74 1.09797 0.908781 169.318 135.356 -1 1289121 17 4.60155e+08 3.01448e+08 3.17281e+08 22033.4 108.23 234.326 190.185 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 42560.88 vpr 6.35 GiB -1 -1 1060.82 2104648 4 35779.24 -1 -1 1168924 -1 -1 15289 652 458 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6658128 652 578 587833 538751 1 142046 17388 168 168 28224 dsp_top auto 3792.2 MiB 1334.50 2402446 32440572 13681743 17973716 785113 5856.8 MiB 1927.66 10.89 6.9964 -921673 -6.9964 6.9964 34.97 2.51671 1.97649 373.17 302.896 -1 2735850 16 9.07771e+08 5.93977e+08 6.21411e+08 22017.1 228.75 493.742 407.089 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 79534.09 vpr 9.24 GiB -1 -1 1581.99 3213072 4 69583.96 -1 -1 1763048 -1 -1 22846 652 679 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9688232 652 866 876458 803425 1 211260 25656 200 200 40000 dsp_top auto 5580.4 MiB 2073.77 4237568 55245338 23267923 30805131 1172284 8437.3 MiB 2868.84 15.36 8.07111 -1.60215e+06 -8.07111 8.07111 54.87 2.67554 2.06921 438.894 351.141 -1 4656710 14 1.28987e+09 8.86534e+08 8.79343e+08 21983.6 469.61 576.631 470.505 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 7689.40 vpr 3.44 GiB -1 -1 194.63 777948 6 1403.65 -1 -1 437312 -1 -1 4092 2642 303 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3603292 2642 19 212442 171300 1 106038 7384 150 150 22500 dsp_top auto 1249.4 MiB 2854.92 1241963 11578776 4386534 6865036 327206 3518.8 MiB 1000.45 6.04 6.68343 -382062 -6.68343 6.68343 30.21 1.16251 1.00997 191.637 158.755 -1 1789984 16 7.19123e+08 2.39135e+08 4.96675e+08 22074.4 125.26 248.159 206.707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 3977.34 vpr 1.87 GiB -1 -1 45.24 221264 4 2135.30 -1 -1 128584 -1 -1 1997 691 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 1957860 691 1109 58270 53285 1 21332 3997 118 118 13924 dsp_top auto 374.1 MiB 48.49 769778 4760047 2439645 1886693 433709 1912.0 MiB 161.22 1.18 4.52129 -112279 -4.52129 4.52129 17.21 0.247567 0.208808 40.0291 33.1037 -1 899573 14 4.42318e+08 1.0648e+08 3.07116e+08 22056.6 59.14 51.6708 43.422 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 13035.34 vpr 8.60 GiB -1 -1 116.08 558336 5 5939.66 -1 -1 343824 -1 -1 1527 643 64 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9021472 643 545 87276 60173 2 42285 3820 264 264 69696 dsp_top auto 636.4 MiB 131.95 1846694 4988603 2040889 1701576 1246138 8810.0 MiB 428.90 3.30 7.99244 -359520 -7.99244 2.49651 108.96 0.533221 0.473465 91.6575 81.0528 -1 1934790 14 2.25492e+09 3.15602e+08 1.53035e+09 21957.6 262.46 118.592 105.973 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 10727.27 vpr 8.60 GiB -1 -1 126.24 637616 6 3082.05 -1 -1 340524 -1 -1 1841 645 116 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9015404 645 545 74887 56850 2 37369 4189 264 264 69696 dsp_top auto 635.8 MiB 491.72 839427 5742369 2085420 2345678 1311271 8804.1 MiB 571.81 2.60 9.05136 -267977 -9.05136 2.90326 126.04 0.567778 0.484788 111.703 95.5517 -1 1012032 15 2.25492e+09 3.31776e+08 1.53035e+09 21957.6 99.83 137.216 118.724 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 41748.68 vpr 34.21 GiB -1 -1 510.65 1503084 4 8403.24 -1 -1 564740 -1 -1 4061 21 9017 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 35874916 21 26 134105 127284 1 74579 13230 534 534 285156 memory auto 1579.3 MiB 4307.58 3784413 24724904 11411532 13231909 81463 35034.1 MiB 1279.62 10.26 14.1413 -1.81655e+06 -14.1413 14.1413 739.03 1.34387 1.09455 266.464 207.554 -1 4268880 13 9.28675e+09 1.38138e+09 6.26248e+09 21961.6 260.08 337.454 266.707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 903.56 parmys 2.13 GiB -1 -1 902.69 2234920 7 39391.43 -1 -1 841608 -1 -1 9907 21 3438 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 15035832 21 26 296275 279040 1 140389 13782 330 330 108900 memory auto 2543.1 MiB 9101.84 2817791 23136602 9815610 13166345 154647 14683.4 MiB 1808.92 11.72 10.5747 -3.03149e+06 -10.5747 10.5747 211.40 2.75628 2.09374 394.038 303.728 -1 4119240 14 3.52886e+09 8.48708e+08 2.39067e+09 21952.9 259.29 508.636 401.153 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 34139.57 vpr 4.49 GiB -1 -1 470.72 1559216 6 19481.17 -1 -1 908648 -1 -1 9003 410 312 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 4704620 410 25 390374 333136 1 165673 10118 152 152 23104 dsp_top auto 2433.9 MiB 10038.59 2070901 15105386 6222455 8459421 423510 4366.6 MiB 1923.39 11.05 5.57792 -432811 -5.57792 5.57792 31.07 1.55012 1.18787 239.087 191.106 -1 2691411 17 7.41832e+08 3.87561e+08 5.09338e+08 22045.4 414.99 329.802 268.937 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/config.txt similarity index 79% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/config.txt index eb469354721..ff57ba0bafb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/config.txt @@ -13,16 +13,7 @@ archs_dir=arch/COFFE_22nm # Some of these benchmarks are designs with hard dsp and ram blocks # but in this task, we're running them without enabling these # blocks (that is, the macro `complex_dsp` and `hard_mem` are not defined). -circuit_list_add=proxy.2.v -circuit_list_add=tdarknet_like.large.v -circuit_list_add=proxy.4.v -circuit_list_add=proxy.1.v -circuit_list_add=bwave_like.float.large.v -circuit_list_add=proxy.3.v circuit_list_add=lenet.v -circuit_list_add=deepfreeze.style1.sv -circuit_list_add=deepfreeze.style2.sv -circuit_list_add=deepfreeze.style3.sv circuit_list_add=clstm_like.small.v circuit_list_add=clstm_like.medium.v circuit_list_add=clstm_like.large.v @@ -33,7 +24,6 @@ circuit_list_add=tpu_like.large.ws.v circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v -circuit_list_add=dla_like.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/golden_results.txt new file mode 100644 index 00000000000..5aecb876aaa --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb/config/golden_results.txt @@ -0,0 +1,12 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 6512.03 parmys 6.81 GiB -1 -1 2803.15 7141204 8 3272.22 -1 -1 229632 -1 -1 1215 3 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 406888 3 73 29130 23346 1 13644 1292 40 40 1600 clb auto 246.5 MiB 63.14 136280 627318 185500 408250 33568 357.6 MiB 85.00 0.86 8.27929 -16089.3 -8.27929 8.27929 1.13 0.12917 0.113598 13.8302 11.3301 -1 224227 19 4.87982e+07 3.41577e+07 3.42310e+07 21394.3 19.69 22.8327 18.7232 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 17199.48 vpr 3.24 GiB -1 -1 583.78 1084852 4 13572.40 -1 -1 606412 -1 -1 7731 652 237 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3400564 652 290 299239 274094 1 72874 9119 120 120 14400 dsp_top auto 1946.4 MiB 725.17 1086525 13721951 5750436 7628104 343411 3000.6 MiB 920.88 5.92 6.3706 -404576 -6.3706 6.3706 16.00 1.30631 1.07494 208.425 167.37 -1 1308179 19 4.60155e+08 3.01393e+08 3.17281e+08 22033.4 125.07 285.633 232.404 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 44836.58 vpr 6.35 GiB -1 -1 1206.67 2108616 4 37270.70 -1 -1 1168924 -1 -1 15290 652 460 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6654212 652 578 587830 538748 1 142127 17391 168 168 28224 dsp_top auto 3784.4 MiB 1272.33 2541145 33348915 14048448 18476269 824198 5852.2 MiB 2378.39 15.56 6.83162 -1.04508e+06 -6.83162 6.83162 36.38 2.58887 2.22298 379.541 301.913 -1 2865108 16 9.07771e+08 5.9428e+08 6.21411e+08 22017.1 283.80 506.773 410.065 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 79425.36 vpr 9.26 GiB -1 -1 1997.66 3183680 4 68911.59 -1 -1 1763240 -1 -1 22848 652 682 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9708760 652 866 876471 803438 1 211268 25661 200 200 40000 dsp_top auto 5596.5 MiB 2037.93 4249390 55259651 23005638 31099607 1154406 8453.4 MiB 2762.94 28.11 7.65321 -1.56393e+06 -7.65321 7.65321 50.04 2.65623 2.07346 405.053 322.505 -1 4619796 15 1.28987e+09 8.87003e+08 8.79343e+08 21983.6 963.02 568.098 461.604 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 7473.84 vpr 3.43 GiB -1 -1 212.26 778664 7 1222.45 -1 -1 441748 -1 -1 4105 2642 303 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 3596256 2642 19 212323 171183 1 106097 7397 150 150 22500 dsp_top auto 1242.7 MiB 2912.94 1231807 11750080 4389654 7016159 344267 3512.0 MiB 847.80 4.34 7.23783 -354254 -7.23783 7.23783 35.98 0.918396 0.749614 172.334 143.707 -1 1767908 14 7.19123e+08 2.39497e+08 4.96675e+08 22074.4 118.24 223.25 185.927 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 66126.70 vpr 6.47 GiB -1 -1 1562.91 4922508 8 55669.26 -1 -1 1107228 -1 -1 21633 691 0 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 6783796 691 1109 541681 488696 1 246413 23533 160 160 25600 clb auto 3991.5 MiB 1475.14 3658232 41820833 17178641 23398798 1243394 5591.4 MiB 3905.43 22.04 9.62737 -577135 -9.62737 9.62737 30.29 2.21008 1.72089 295.048 237.971 -1 4698140 16 8.16705e+08 6.29026e+08 5.64874e+08 22065.4 1453.16 415.661 341.759 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 19152.46 vpr 8.85 GiB -1 -1 479.24 773124 5 9646.24 -1 -1 475184 -1 -1 4147 643 64 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9279656 643 545 176558 144751 2 82400 6440 264 264 69696 dsp_top auto 1047.5 MiB 2257.70 1886822 10367410 4165781 5677172 524457 9062.2 MiB 625.09 2.79 9.68339 -449286 -9.68339 3.00291 122.05 0.627968 0.528543 125.251 100.638 -1 2231844 14 2.25492e+09 3.88712e+08 1.53035e+09 21957.6 75.18 155.946 127.105 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 25351.94 vpr 8.98 GiB -1 -1 264.56 848708 6 16499.07 -1 -1 435432 -1 -1 4888 645 116 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 9418912 645 545 198334 173097 2 76208 7236 264 264 69696 dsp_top auto 1280.7 MiB 1663.77 2097031 10361020 4450611 5586968 323441 9198.2 MiB 743.86 4.12 9.54793 -764213 -9.54793 2.98183 123.12 0.886964 0.686876 142.62 112.098 -1 2456755 18 2.25492e+09 4.16799e+08 1.53035e+09 21957.6 134.09 191.54 153.367 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 46496.67 vpr 34.29 GiB -1 -1 1002.01 1826968 9 14701.65 -1 -1 600168 -1 -1 4820 21 9017 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 35960132 21 26 151732 142419 1 82839 13901 534 534 285156 memory auto 1714.1 MiB 2899.06 3638215 27078917 12451772 14536901 90244 35117.3 MiB 1593.90 8.17 13.0411 -1.80913e+06 -13.0411 13.0411 756.10 2.03882 1.51017 352.692 271.908 -1 4218468 13 9.28675e+09 1.38022e+09 6.26248e+09 21961.6 271.58 433.418 339.71 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 60670.28 parmys 4.27 GiB -1 -1 2068.30 4479388 10 58408.16 -1 -1 985016 -1 -1 -1 -1 -1 -1 exited with return code 1 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 296152 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 34977.09 vpr 4.75 GiB -1 -1 532.62 1673200 6 19849.28 -1 -1 1005464 -1 -1 10143 410 312 -1 success 9c0df2e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-03T14:49:57 mustang /homes/vtr-verilog-to-routing 4982696 410 25 447261 375335 1 185950 11258 152 152 23104 dsp_top auto 2697.4 MiB 10488.65 2533677 17541799 7360455 9848351 332993 4523.6 MiB 1992.58 12.29 10.5402 -463530 -10.5402 10.5402 28.38 1.27474 1.07805 200.671 162.147 -1 3264297 18 7.41832e+08 4.19372e+08 5.09338e+08 22045.4 276.77 292.19 239.644 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/config.txt similarity index 97% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/config.txt index 9d83c8bab7d..90978863470 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/config.txt @@ -13,6 +13,7 @@ archs_dir=arch/COFFE_22nm # Some of these benchmarks are designs with hard dsp and ram blocks # but in this task, we're running them without enabling these # blocks (that is, the macro `complex_dsp` and `hard_mem` are not defined). +circuit_list_add=lenet.v circuit_list_add=clstm_like.small.v circuit_list_add=clstm_like.medium.v circuit_list_add=clstm_like.large.v @@ -23,7 +24,6 @@ circuit_list_add=tpu_like.large.ws.v circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v -circuit_list_add=dla_like.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/golden_results.txt new file mode 100644 index 00000000000..88ab0da6cb5 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_no_hb_odin/config/golden_results.txt @@ -0,0 +1,12 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 38.46 odin 863.44 MiB -1 884160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 139 unknown unknown unknown unknown mustang /homes/koios -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 39850.62 vpr 4.68 GiB 273.12 2323432 -1 -1 3 27173.68 -1 -1 1284236 -1 -1 9622 652 257 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 4911360 652 290 386136 345502 1 107486 11182 152 152 23104 dsp_top auto 2725.2 MiB 7700.33 1485358 18508962 7808125 10191387 509450 4579.7 MiB 1549.46 7.52 6.64467 -489713 -6.64467 6.64467 37.34 2.10276 1.54318 320.538 251.106 -1 1773877 18 7.41832e+08 3.95486e+08 5.09338e+08 22045.4 187.30 430.947 343.755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 97916.46 vpr 8.70 GiB 775.53 4356876 -1 -1 3 74105.34 -1 -1 2480996 -1 -1 18138 652 498 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 9125376 652 578 717372 645140 1 193704 20527 206 206 42436 dsp_top auto 5058.4 MiB 16754.43 3332292 41035869 16711502 23767621 556746 8463.2 MiB 2340.73 13.33 8.83497 -1.22358e+06 -8.83497 8.83497 59.94 2.45875 1.92853 369.874 301.329 -1 3772322 19 1.36407e+09 7.42426e+08 9.33443e+08 21996.5 281.68 509.236 420.889 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 172578.55 vpr 12.63 GiB 1841.77 6358576 -1 -1 3 136423.34 -1 -1 3500012 -1 -1 26627 652 739 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 13246832 652 866 1048088 944258 1 279231 29845 248 248 61504 dsp_top auto 7370.9 MiB 25249.42 5603248 69900112 29840995 38764452 1294665 12167.6 MiB 3576.90 18.63 8.83497 -1.99261e+06 -8.83497 8.83497 84.64 3.45625 2.69064 572.539 449.327 -1 6070349 18 1.98856e+09 1.08862e+09 1.35071e+09 21961.3 618.99 767.309 616.832 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 67093.21 vpr 5.82 GiB 49.67 663460 -1 -1 7 56120.62 -1 -1 652944 -1 -1 5866 2658 305 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 6102112 2658 19 279802 231091 1 125699 9458 200 200 40000 dsp_top auto 1742.4 MiB 6550.86 1791485 14906031 5970429 8435424 500178 5959.1 MiB 1044.59 6.69 7.98145 -482294 -7.98145 7.98145 60.69 1.71391 1.3895 229.361 183.336 -1 2325331 14 1.28987e+09 3.60476e+08 8.79343e+08 21983.6 118.21 288.388 234.107 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 106644.13 vpr 7.20 GiB 1828.12 4220940 -1 -1 7 94244.54 -1 -1 1659824 -1 -1 23732 691 0 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 7550476 691 1088 606852 532218 1 254293 25611 167 167 27889 clb auto 4535.0 MiB 1382.44 3549786 47946902 19988553 26173665 1784684 6208.3 MiB 5287.91 51.17 8.90481 -545352 -8.90481 8.90481 33.07 3.52881 3.02463 484.798 397.109 -1 4595810 15 8.91806e+08 6.87596e+08 6.14936e+08 22049.4 1545.05 637.839 529.298 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 38324.46 vpr 8.90 GiB 102.94 800972 -1 -1 5 26925.53 -1 -1 539616 -1 -1 4332 643 64 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 9334828 643 545 179742 147894 2 83253 6648 264 264 69696 dsp_top auto 1117.0 MiB 1737.07 2298057 9316615 4002390 5024831 289394 9116.0 MiB 814.45 5.40 9.53687 -516489 -9.53687 3.15409 154.98 0.85611 0.667034 135.523 104.637 -1 2681558 15 2.25492e+09 3.99711e+08 1.53035e+09 21957.6 124.34 176.302 139.057 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 27035.60 vpr 8.75 GiB 565.06 1018968 -1 -1 10 11621.67 -1 -1 396896 -1 -1 4267 645 116 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 9179116 645 545 138495 112860 2 66328 6638 264 264 69696 dsp_top auto 929.3 MiB 1200.11 1056249 10794572 4218936 5680878 894758 8964.0 MiB 909.01 4.86 10.7715 -341206 -10.7715 5.74836 167.53 0.869498 0.723813 163.458 131.879 -1 1325232 17 2.25492e+09 4.05308e+08 1.53035e+09 21957.6 96.74 205.926 167.659 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 55329.50 vpr 16.01 GiB 1650.95 1941752 -1 -1 7 34119.50 -1 -1 828156 -1 -1 7879 21 3978 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 16789140 21 25 163861 153498 1 85744 11919 356 356 126736 memory auto 1934.2 MiB 1749.77 1935053 23282967 10285144 11437908 1559915 16395.6 MiB 1929.16 10.50 17.6419 -3.84745e+06 -17.6419 17.6419 303.14 2.81287 2.41276 449.029 367.054 -1 2797459 14 4.10542e+09 7.71545e+08 2.78303e+09 21959.3 239.66 557.597 459.649 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 181203.52 vpr 18.79 GiB 6014.44 5365364 -1 -1 7 156428.87 -1 -1 1929748 -1 -1 17767 21 4400 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 19706508 21 25 446064 410922 1 206422 22280 372 372 138384 memory auto 4181.9 MiB 4466.84 3290168 51413484 22226010 27217825 1969649 19244.6 MiB 3352.38 15.92 11.7382 -3.36286e+06 -11.7382 11.7382 262.83 2.65608 2.21533 502.8 395.161 -1 4704832 18 4.48577e+09 1.1185e+09 3.03875e+09 21958.8 270.81 654.535 524.302 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 58108.52 vpr 5.76 GiB 573.49 1683720 -1 -1 5 46362.96 -1 -1 1450036 -1 -1 13520 410 384 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 6037672 410 25 554046 446832 1 234009 14739 162 162 26244 dsp_top auto 3433.2 MiB 5304.32 2363986 27831605 11380325 15324157 1127123 5359.3 MiB 3159.89 16.60 10.0466 -409749 -10.0466 10.0466 34.22 2.32422 1.86821 382.391 315.269 -1 3065873 17 8.36692e+08 5.31636e+08 5.79090e+08 22065.6 218.83 487.398 405.578 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/config.txt similarity index 97% rename from vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/config.txt index 9410c990af8..8b8f8ed4a2c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/config.txt @@ -13,6 +13,7 @@ archs_dir=arch/COFFE_22nm includes_dir=benchmarks/verilog/koios # Add circuits to list to sweep +circuit_list_add=lenet.v circuit_list_add=clstm_like.small.v circuit_list_add=clstm_like.medium.v circuit_list_add=clstm_like.large.v @@ -23,7 +24,6 @@ circuit_list_add=tpu_like.large.ws.v circuit_list_add=tdarknet_like.small.v circuit_list_add=tdarknet_like.large.v circuit_list_add=dla_like.medium.v -circuit_list_add=dla_like.large.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/golden_results.txt new file mode 100644 index 00000000000..d4b600655a3 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_large_odin/config/golden_results.txt @@ -0,0 +1,12 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lenet.v common 39.24 odin 863.62 MiB -1 884348 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 139 unknown unknown unknown unknown mustang /homes/koios -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 32204.37 vpr 4.61 GiB 269.20 2306988 -1 -1 3 26737.23 -1 -1 1267968 -1 -1 9395 652 257 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 4832436 652 290 377550 336903 1 99104 10955 152 152 23104 dsp_top auto 2661.0 MiB 780.35 1377306 18374669 7784879 10078997 510793 4540.9 MiB 1598.94 8.24 6.95757 -456349 -6.95757 6.95757 34.16 2.07942 1.61777 317.115 255.286 -1 1645889 13 7.41832e+08 3.89152e+08 5.09338e+08 22045.4 140.54 405.15 330.381 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 90977.10 vpr 8.57 GiB 688.29 4332360 -1 -1 3 81665.15 -1 -1 2453384 -1 -1 17856 652 498 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 8986696 652 578 703878 631620 1 180522 20245 206 206 42436 dsp_top auto 4945.0 MiB 1683.44 3224944 42216574 18180560 23361348 674666 8395.5 MiB 2628.77 13.73 8.20917 -1.29474e+06 -8.20917 8.20917 62.58 2.89675 2.17457 448.383 357.835 -1 3601143 18 1.36407e+09 7.34557e+08 9.33443e+08 21996.5 355.61 596.477 484.799 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 156167.70 vpr 12.59 GiB 1385.85 6309288 -1 -1 3 143089.23 -1 -1 3453768 -1 -1 26337 652 739 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 13196588 652 866 1030248 926379 1 261968 29555 248 248 61504 dsp_top auto 7324.9 MiB 2674.89 5185030 69909551 29459982 38951560 1498009 12196.2 MiB 3483.37 18.70 8.71698 -1.81703e+06 -8.71698 8.71698 84.19 3.39856 2.63319 536.954 429.469 -1 5659103 15 1.98856e+09 1.08053e+09 1.35071e+09 21961.3 710.36 712.59 579.726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 60554.13 vpr 5.70 GiB 45.86 612228 -1 -1 7 51856.39 -1 -1 604480 -1 -1 5059 2658 305 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 5979524 2658 19 252798 204085 1 121009 8651 200 200 40000 dsp_top auto 1578.6 MiB 4896.35 1655967 14033995 5640023 7834255 559717 5839.4 MiB 780.25 4.06 6.82952 -459396 -6.82952 6.82952 54.51 1.27099 1.00572 205.507 163.64 -1 2176966 16 1.28987e+09 3.37958e+08 8.79343e+08 21983.6 111.53 259.246 209.517 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 7390.96 vpr 1.88 GiB 20.07 221156 -1 -1 4 4438.23 -1 -1 145092 -1 -1 2000 691 0 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 1972284 691 1088 58320 53286 1 21339 3979 118 118 13924 dsp_top auto 389.8 MiB 60.65 650249 4763046 2391727 1934372 436947 1926.1 MiB 349.18 2.88 4.55054 -111953 -4.55054 4.55054 23.11 0.57716 0.469385 73.0068 60.4186 -1 779806 12 4.42318e+08 1.06564e+08 3.07116e+08 22056.6 74.09 92.3058 76.8147 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 30228.16 vpr 8.74 GiB 3365.76 781668 -1 -1 5 14910.26 -1 -1 379732 -1 -1 1597 643 64 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 9164360 643 545 88415 61271 2 43017 3913 264 264 69696 dsp_top auto 943.4 MiB 250.93 1902587 5212831 2177939 1792538 1242354 8949.6 MiB 942.01 6.50 8.60443 -355743 -8.60443 2.42096 146.49 1.08318 0.956868 201.741 179.864 -1 2005910 14 2.25492e+09 3.23392e+08 1.53035e+09 21957.6 101.30 252.563 227.158 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 24558.97 vpr 8.76 GiB 4920.61 1003420 -1 -1 8 8853.58 -1 -1 389052 -1 -1 3001 645 116 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 9188104 645 545 92461 73957 2 54463 5373 264 264 69696 dsp_top auto 871.6 MiB 384.77 867446 8613693 3510982 3156691 1946020 8972.8 MiB 1031.41 6.90 8.58916 -280870 -8.58916 2.82816 147.88 0.896941 0.790746 185.778 161.64 -1 1035539 18 2.25492e+09 3.70236e+08 1.53035e+09 21957.6 211.23 237.647 208.665 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 51676.92 vpr 15.89 GiB 1445.71 1391572 -1 -1 6 30521.02 -1 -1 708500 -1 -1 6988 21 3978 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 16656720 21 25 145363 138464 1 76281 11102 356 356 126736 memory auto 1750.3 MiB 2285.42 1822095 20561072 9166825 9914418 1479829 16266.3 MiB 1749.58 9.63 13.0415 -3.80464e+06 -13.0415 13.0415 299.41 2.745 2.10802 465.483 358.88 -1 2655927 14 4.10542e+09 7.65462e+08 2.78303e+09 21959.3 259.78 573.352 448.458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 140289.26 vpr 18.26 GiB 4298.49 3050196 -1 -1 5 113632.28 -1 -1 1455328 -1 -1 13534 21 4400 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 19147184 21 25 356726 338400 1 158062 18347 372 372 138384 memory auto 3326.0 MiB 7267.85 3121428 43071029 18350489 22687670 2032870 18698.4 MiB 2862.44 13.78 13.5169 -3.61828e+06 -13.5169 13.5169 272.13 2.89166 2.41693 581.602 467.324 -1 4308562 17 4.48577e+09 1.07651e+09 3.03875e+09 21958.8 290.19 733.794 596.308 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 55877.12 vpr 5.29 GiB 488.24 1511776 -1 -1 5 44316.06 -1 -1 1283240 -1 -1 10617 410 312 -1 success d1480fe release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T12:18:30 mustang /homes/koios 5543440 410 25 475238 385544 1 195499 11764 162 162 26244 dsp_top auto 2986.5 MiB 5444.03 2212785 18065719 7526438 9719580 819701 5111.1 MiB 2641.06 14.21 5.16212 -466728 -5.16212 5.16212 32.89 2.24012 1.90319 347.549 284.139 -1 2892193 17 8.36692e+08 4.40719e+08 5.79090e+08 22065.6 273.06 451.76 372.387 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/golden_results.txt deleted file mode 100644 index 5765abf2961..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_no_hard_block_odin/config/golden_results.txt +++ /dev/null @@ -1,12 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 11134.93 vpr 4.66 GiB 155.71 2339140 -1 -1 3 4755.43 -1 -1 1283796 -1 -1 9628 652 257 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 4887868 652 290 386136 345502 1 108240 11188 152 152 23104 dsp_top auto 2716.4 MiB 4759.45 -1 4535.6 MiB 429.71 2.48 7.27047 -524204 -7.27047 7.27047 13.91 0.64945 0.535262 110.99 87.5764 -1 1765111 19 7.41832e+08 3.95653e+08 5.09338e+08 22045.4 66.49 152.364 124.254 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 34605.71 vpr 8.65 GiB 341.45 4385996 -1 -1 3 20581.68 -1 -1 2416012 -1 -1 18138 652 498 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 9065148 652 578 717372 645140 1 194208 20527 206 206 42436 dsp_top auto 5034.4 MiB 10558.20 -1 8368.3 MiB 1115.12 5.87 8.83497 -1.1807e+06 -8.83497 8.83497 30.86 1.23284 1.02144 218.966 172.956 -1 3737763 16 1.36407e+09 7.42426e+08 9.33443e+08 21996.5 128.26 290.181 236.273 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 74868.94 vpr 12.59 GiB 616.03 6387516 -1 -1 3 52653.14 -1 -1 3544964 -1 -1 26627 652 739 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 13201844 652 866 1048088 944258 1 280519 29845 248 248 61504 dsp_top auto 7370.5 MiB 16485.24 -1 12050.6 MiB 1928.01 10.16 9.14787 -2.01312e+06 -9.14787 9.14787 47.80 2.0023 1.53276 328.858 258.605 -1 5994065 17 1.98856e+09 1.08862e+09 1.35071e+09 21961.3 388.95 439.19 356.647 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 19400.24 vpr 5.74 GiB 29.04 669896 -1 -1 7 13241.44 -1 -1 652444 -1 -1 5870 2658 305 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 6014672 2658 19 279802 231091 1 125892 9462 200 200 40000 dsp_top auto 1736.0 MiB 4072.16 -1 5873.7 MiB 469.53 2.63 7.84104 -489879 -7.84104 7.84104 32.50 0.662545 0.517645 109.777 85.8291 -1 2252600 15 1.28987e+09 3.60588e+08 8.79343e+08 21983.6 56.45 140.032 112.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 33383.26 vpr 7.14 GiB 398.50 4228260 -1 -1 7 26478.56 -1 -1 1680344 -1 -1 23738 691 0 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 7486624 691 1088 606852 532218 1 255084 25617 167 167 27889 clb auto 4529.3 MiB 831.84 -1 6151.2 MiB 2505.80 18.86 9.39166 -552384 -9.39166 9.39166 18.49 1.47907 1.14892 211.489 166.266 -1 4701836 15 8.91806e+08 6.87764e+08 6.14936e+08 22049.4 1844.68 284.629 230.676 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 9153.78 vpr 8.78 GiB 56.34 806504 -1 -1 5 4695.24 -1 -1 539600 -1 -1 4334 643 64 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 9206152 643 545 179742 147894 2 83913 6650 264 264 69696 dsp_top auto 1113.1 MiB 1156.62 -1 8990.4 MiB 264.15 1.46 9.74477 -524147 -9.74477 4.2014 62.08 0.329622 0.262375 56.434 44.3012 -1 2360715 15 2.25492e+09 3.99767e+08 1.53035e+09 21957.6 40.41 73.3256 59.2641 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 6236.96 vpr 8.63 GiB 263.24 1029960 -1 -1 10 2178.45 -1 -1 398652 -1 -1 4311 645 116 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 9045632 645 545 138495 112860 2 66010 6682 264 264 69696 dsp_top auto 923.0 MiB 320.32 -1 8833.6 MiB 347.75 1.42 9.93607 -347841 -9.93607 3.43117 63.71 0.303836 0.242251 75.8109 59.2674 -1 1344865 17 2.25492e+09 4.06536e+08 1.53035e+09 21957.6 31.12 91.9118 73.3083 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 17719.88 vpr 15.78 GiB 721.78 1982860 -1 -1 7 9477.54 -1 -1 827300 -1 -1 7886 21 3978 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 16545532 21 25 163861 153498 1 85838 11926 356 356 126736 memory auto 1912.9 MiB 1073.74 -1 16157.7 MiB 1019.47 3.90 13.3385 -3.4504e+06 -13.3385 13.3385 134.66 1.00357 0.827119 261.031 202.59 -1 2836034 14 4.10542e+09 7.71741e+08 2.78303e+09 21959.3 86.85 305.115 241.338 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 83296.38 vpr 18.56 GiB 2532.90 5466436 -1 -1 7 67754.53 -1 -1 1929668 -1 -1 17806 21 4400 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 19466260 21 25 446064 410922 1 206809 22319 372 372 138384 memory auto 4196.9 MiB 2913.66 -1 19010.0 MiB 2658.55 13.30 11.7382 -3.48746e+06 -11.7382 11.7382 180.06 1.88724 1.54655 365.866 285.178 -1 4655457 17 4.48577e+09 1.11958e+09 3.03875e+09 21958.8 174.29 466.029 372.92 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 21333.08 vpr 5.71 GiB 168.99 1707908 -1 -1 5 14100.21 -1 -1 1454844 -1 -1 13534 410 384 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 5989508 410 25 554046 446832 1 233694 14753 162 162 26244 dsp_top auto 3441.3 MiB 3509.35 -1 5319.4 MiB 1953.77 9.40 10.6724 -419078 -10.6724 10.6724 21.33 1.26785 0.99504 221.686 176.947 -1 3187859 20 8.36692e+08 5.32027e+08 5.79090e+08 22065.6 164.55 287.515 234.164 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.large.v common 134856.76 vpr 16.75 GiB 1132.68 4908976 -1 -1 5 106982.59 -1 -1 4042520 -1 -1 34215 818 1536 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 17563212 818 49 1551360 1278310 1 634823 37994 296 296 87616 dsp_top auto 9373.6 MiB 7660.57 -1 16409.5 MiB 6451.95 43.76 11.9084 -1.89814e+06 -11.9084 11.9084 102.15 4.29637 3.33007 574.797 456.576 -1 12409271 20 2.83782e+09 1.51539e+09 1.92343e+09 21953.0 7980.73 766.36 620.329 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/golden_results.txt deleted file mode 100644 index 43f13f5c438..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_odin/config/golden_results.txt +++ /dev/null @@ -1,12 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.small.v common 8888.04 vpr 4.58 GiB 171.00 2327892 -1 -1 3 6377.96 -1 -1 1271616 -1 -1 9396 652 257 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 4806272 652 290 377550 336903 1 99045 10956 152 152 23104 dsp_top auto 2651.3 MiB 419.98 -1 4492.8 MiB 614.85 3.75 7.27047 -547406 -7.27047 7.27047 17.00 0.728059 0.608428 128.075 102.015 -1 1674601 17 7.41832e+08 3.8918e+08 5.09338e+08 22045.4 71.34 171.96 140.604 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.medium.v common 33016.37 vpr 8.52 GiB 384.49 4362036 -1 -1 3 27518.14 -1 -1 2453208 -1 -1 17854 652 498 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 8936564 652 578 703878 631620 1 180414 20243 206 206 42436 dsp_top auto 4934.4 MiB 1002.03 -1 8299.3 MiB 1494.38 9.50 8.20917 -1.27546e+06 -8.20917 8.20917 38.32 1.79649 1.3909 260.168 204.535 -1 3560917 15 1.36407e+09 7.34501e+08 9.33443e+08 21996.5 210.56 346.677 280.878 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml clstm_like.large.v common 73110.77 vpr 12.51 GiB 649.67 6352020 -1 -1 3 64584.90 -1 -1 3506612 -1 -1 26335 652 739 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 13115708 652 866 1030248 926379 1 262738 29553 248 248 61504 dsp_top auto 7324.3 MiB 1825.25 -1 12043.4 MiB 2461.95 11.75 9.46077 -1.74477e+06 -9.46077 9.46077 55.48 2.16105 1.67156 378.6 299.216 -1 5583309 19 1.98856e+09 1.08047e+09 1.35071e+09 21961.3 320.76 508.383 412.887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml lstm.v common 21565.20 vpr 5.64 GiB 26.97 616932 -1 -1 7 15780.61 -1 -1 609420 -1 -1 5060 2658 305 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 5914224 2658 19 252798 204085 1 121194 8652 200 200 40000 dsp_top auto 1570.3 MiB 3235.28 -1 5775.6 MiB 528.72 2.94 6.8583 -461006 -6.8583 6.8583 38.19 0.72106 0.562893 119.016 95.9425 -1 2172928 14 1.28987e+09 3.37986e+08 8.79343e+08 21983.6 58.59 149.22 122.572 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 1527.03 vpr 1.85 GiB 11.76 227772 -1 -1 4 878.64 -1 -1 144832 -1 -1 2001 691 0 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 1942584 691 1088 58320 53286 1 21345 3980 118 118 13924 dsp_top auto 386.2 MiB 29.57 -1 1897.1 MiB 94.99 0.64 4.55054 -113212 -4.55054 4.55054 9.11 0.11558 0.0962024 25.1295 20.8727 -1 777736 11 4.42318e+08 1.06592e+08 3.07116e+08 22056.6 16.67 29.9856 25.3523 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.os.v common 7445.27 vpr 8.61 GiB 1371.06 791892 -1 -1 5 2396.32 -1 -1 382128 -1 -1 1597 643 64 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 9033000 643 545 88415 61271 2 42935 3913 264 264 69696 dsp_top auto 939.8 MiB 98.91 -1 8821.3 MiB 646.15 2.54 8.57943 -394841 -8.57943 2.62424 67.05 0.647449 0.589208 191.43 174.316 -1 2057764 16 2.25492e+09 3.23392e+08 1.53035e+09 21957.6 62.19 225.34 206.708 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.large.ws.v common 6912.81 vpr 8.64 GiB 1937.80 1014892 -1 -1 8 1100.35 -1 -1 388208 -1 -1 3006 645 116 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 9058420 645 545 92461 73957 2 54477 5378 264 264 69696 dsp_top auto 867.7 MiB 235.79 -1 8846.1 MiB 632.61 2.42 9.46748 -258748 -9.46748 2.96924 69.88 0.496757 0.437445 158.129 138.398 -1 980147 16 2.25492e+09 3.70375e+08 1.53035e+09 21957.6 60.64 183.811 162.58 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.small.v common 15916.85 vpr 15.65 GiB 626.53 1410360 -1 -1 6 7500.18 -1 -1 708340 -1 -1 6978 21 3978 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 16408312 21 25 145363 138464 1 75860 11092 356 356 126736 memory auto 1746.0 MiB 1320.69 -1 16023.7 MiB 968.67 4.03 12.4112 -4.11494e+06 -12.4112 12.4112 147.07 0.998064 0.820581 255.838 200.593 -1 2728542 15 4.10542e+09 7.65183e+08 2.78303e+09 21959.3 94.51 299.902 238.821 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tdarknet_like.large.v common 80108.78 vpr 18.04 GiB 1874.11 3073752 -1 -1 5 64772.74 -1 -1 1454696 -1 -1 13575 21 4400 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 18913568 21 25 356726 338400 1 157423 18388 372 372 138384 memory auto 3322.0 MiB 4733.64 -1 18470.3 MiB 1871.43 9.15 11.0137 -3.64197e+06 -11.0137 11.0137 166.75 1.46749 1.20276 329.628 256.443 -1 4188961 13 4.48577e+09 1.07766e+09 3.03875e+09 21958.8 134.18 397.25 315.48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.medium.v common 20742.72 vpr 5.23 GiB 132.36 1521516 -1 -1 5 14442.16 -1 -1 1282804 -1 -1 10604 410 312 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 5481160 410 25 475238 385544 1 194901 11751 162 162 26244 dsp_top auto 2983.8 MiB 3526.24 -1 5050.1 MiB 1189.73 6.96 5.16212 -467743 -5.16212 5.16212 19.04 1.10061 0.848006 164.531 128.538 -1 2918539 14 8.36692e+08 4.40357e+08 5.79090e+08 22065.6 127.96 213.729 171.971 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.large.v common 113621.06 vpr 15.20 GiB 857.26 4180136 -1 -1 5 89773.56 -1 -1 3331100 -1 -1 28046 818 864 -1 success v8.0.0-6521-gad23e206c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-4.15.0-124-generic x86_64 2022-10-10T12:22:00 jupiter0 /export/aman/vtr_aman2/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_weekly 15942848 818 49 1276984 1072190 1 498318 31153 296 296 87616 dsp_top auto 7926.4 MiB 6591.82 -1 15517.6 MiB 4972.04 25.99 6.76229 -1.72176e+06 -6.76229 6.76229 95.60 2.89711 2.2958 492.793 387.807 -1 11460538 14 2.83782e+09 1.25073e+09 1.92343e+09 21953.0 7104.45 619.438 500.187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/config.txt new file mode 100644 index 00000000000..fec519a531f --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/config.txt @@ -0,0 +1,45 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios_proxy + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=proxy.1.v +circuit_list_add=proxy.2.v +circuit_list_add=proxy.3.v +circuit_list_add=proxy.4.v +circuit_list_add=proxy.5.v +circuit_list_add=proxy.6.v +circuit_list_add=proxy.7.v +circuit_list_add=proxy.8.v + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Add include files to the list. +# Some benchmarks instantiate hard dsp and memory blocks +# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. +# The hard_block_include.v file +# defines this macros, thereby enabling instantiations of the hard blocks +include_list_add=hard_block_include.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/golden_results.txt new file mode 100644 index 00000000000..2290fe1071c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy/config/golden_results.txt @@ -0,0 +1,9 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.1.v common 30535.22 vpr 9.48 GiB -1 -1 1652.38 3799616 7 2393.26 -1 -1 771680 -1 -1 5817 938 845 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 9940848 938 175 262404 208705 1 137273 8816 264 264 69696 dsp_top auto 1962.1 MiB 17465.99 3242084 14209964 6064078 7558347 587539 9707.9 MiB 2269.49 11.20 8.49902 -576590 -8.49902 8.49902 120.99 1.65144 1.34401 319.238 263.953 -1 4269357 15 2.25492e+09 5.42827e+08 1.53035e+09 21957.6 291.49 414.451 348.422 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.2.v common 49383.26 parmys 7.46 GiB -1 -1 6711.91 7820216 8 22879.15 -1 -1 1478720 -1 -1 8948 318 1105 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 6046424 318 256 373725 328044 1 148054 10957 188 188 35344 memory auto 2466.3 MiB 15021.62 2653372 16311253 6713874 9344147 253232 5904.7 MiB 1439.25 8.76 7.35195 -768561 -7.35195 7.35195 47.97 1.45054 1.22978 225.237 181.257 -1 3431386 18 1.1352e+09 4.85551e+08 7.77871e+08 22008.6 262.44 314.625 258.401 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.3.v common 19852.09 vpr 4.44 GiB -1 -1 2415.20 2344724 9 11508.95 -1 -1 604164 -1 -1 9318 732 846 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 4650536 732 304 284977 256401 1 127990 11307 164 164 26896 memory auto 2050.2 MiB 1517.07 1834702 15487251 6133696 9051915 301640 4541.5 MiB 1750.28 13.38 9.89252 -499927 -9.89252 9.89252 33.45 1.83357 1.60237 215.923 175.904 -1 2500777 18 8.6211e+08 4.03628e+08 5.92859e+08 22042.6 191.91 301.651 247.975 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.4.v common 54152.82 parmys 8.16 GiB -1 -1 5711.77 8560300 7 7695.81 -1 -1 1228588 -1 -1 7685 546 1085 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 7638244 546 1846 328200 285098 1 145315 11924 222 222 49284 dsp_top auto 2318.8 MiB 34102.96 3359643 20028032 8510897 11052028 465107 7459.2 MiB 2454.78 12.61 9.3047 -839575 -9.3047 9.3047 72.17 2.37032 2.07569 353.073 294.754 -1 4470327 15 1.58612e+09 5.57186e+08 1.08358e+09 21986.5 321.00 457.912 387.485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.5.v common 12314.48 vpr 2.72 GiB -1 -1 444.57 1155000 6 6541.48 -1 -1 300412 -1 -1 3183 465 211 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 2847800 465 320 129393 107898 1 58474 4457 136 136 18496 dsp_top auto 844.0 MiB 2964.39 907860 5063951 1987132 2921705 155114 2781.1 MiB 416.84 2.53 7.95731 -241324 -7.95731 7.95731 22.03 0.555623 0.473983 83.803 68.9832 -1 1216557 18 5.92627e+08 1.88417e+08 4.08527e+08 22087.3 77.72 115.317 96.1388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.6.v common 21858.65 vpr 2.98 GiB -1 -1 733.32 1937992 3 1085.26 -1 -1 521520 -1 -1 3399 605 406 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3128500 605 420 162048 138469 1 77337 5130 138 138 19044 dsp_top auto 1117.5 MiB 18099.45 1227614 6196630 2461232 3536309 199089 3055.2 MiB 493.93 4.08 6.60155 -276231 -6.60155 6.60155 22.53 0.699439 0.597719 108.543 88.9515 -1 1702470 17 6.09712e+08 2.26871e+08 4.20597e+08 22085.5 125.59 156.881 130.869 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.7.v common 18763.57 vpr 3.15 GiB -1 -1 819.91 3196296 6 7366.29 -1 -1 557292 -1 -1 4950 354 492 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3303040 354 144 205704 176496 1 87942 6243 138 138 19044 dsp_top auto 1405.3 MiB 7794.25 1515088 7476043 3099214 4331878 44951 3225.6 MiB 827.52 5.11 7.55948 -381034 -7.55948 7.55948 25.21 1.0607 0.89608 155.442 127.043 -1 1992622 16 6.09712e+08 2.82751e+08 4.20597e+08 22085.5 161.80 213.877 177.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.8.v common 13318.28 vpr 3.27 GiB -1 -1 843.59 1554284 6 6540.38 -1 -1 358540 -1 -1 3057 346 235 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3432868 346 656 128390 107845 1 57554 4662 152 152 23104 dsp_top auto 871.1 MiB 2767.71 935474 5766154 2271375 3256584 238195 3352.4 MiB 503.10 3.17 7.72231 -217179 -7.72231 7.72231 35.21 0.741053 0.636728 114.675 96.268 -1 1262212 17 7.41832e+08 2.11044e+08 5.09338e+08 22045.4 88.85 150.569 127.819 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/config.txt new file mode 100644 index 00000000000..8b62b0ff997 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/config.txt @@ -0,0 +1,38 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios_proxy + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=proxy.1.v +circuit_list_add=proxy.2.v +circuit_list_add=proxy.3.v +circuit_list_add=proxy.4.v +circuit_list_add=proxy.5.v +circuit_list_add=proxy.6.v +circuit_list_add=proxy.7.v +circuit_list_add=proxy.8.v + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/golden_results.txt new file mode 100644 index 00000000000..2290fe1071c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_proxy_no_hb/config/golden_results.txt @@ -0,0 +1,9 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.1.v common 30535.22 vpr 9.48 GiB -1 -1 1652.38 3799616 7 2393.26 -1 -1 771680 -1 -1 5817 938 845 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 9940848 938 175 262404 208705 1 137273 8816 264 264 69696 dsp_top auto 1962.1 MiB 17465.99 3242084 14209964 6064078 7558347 587539 9707.9 MiB 2269.49 11.20 8.49902 -576590 -8.49902 8.49902 120.99 1.65144 1.34401 319.238 263.953 -1 4269357 15 2.25492e+09 5.42827e+08 1.53035e+09 21957.6 291.49 414.451 348.422 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.2.v common 49383.26 parmys 7.46 GiB -1 -1 6711.91 7820216 8 22879.15 -1 -1 1478720 -1 -1 8948 318 1105 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 6046424 318 256 373725 328044 1 148054 10957 188 188 35344 memory auto 2466.3 MiB 15021.62 2653372 16311253 6713874 9344147 253232 5904.7 MiB 1439.25 8.76 7.35195 -768561 -7.35195 7.35195 47.97 1.45054 1.22978 225.237 181.257 -1 3431386 18 1.1352e+09 4.85551e+08 7.77871e+08 22008.6 262.44 314.625 258.401 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.3.v common 19852.09 vpr 4.44 GiB -1 -1 2415.20 2344724 9 11508.95 -1 -1 604164 -1 -1 9318 732 846 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 4650536 732 304 284977 256401 1 127990 11307 164 164 26896 memory auto 2050.2 MiB 1517.07 1834702 15487251 6133696 9051915 301640 4541.5 MiB 1750.28 13.38 9.89252 -499927 -9.89252 9.89252 33.45 1.83357 1.60237 215.923 175.904 -1 2500777 18 8.6211e+08 4.03628e+08 5.92859e+08 22042.6 191.91 301.651 247.975 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.4.v common 54152.82 parmys 8.16 GiB -1 -1 5711.77 8560300 7 7695.81 -1 -1 1228588 -1 -1 7685 546 1085 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 7638244 546 1846 328200 285098 1 145315 11924 222 222 49284 dsp_top auto 2318.8 MiB 34102.96 3359643 20028032 8510897 11052028 465107 7459.2 MiB 2454.78 12.61 9.3047 -839575 -9.3047 9.3047 72.17 2.37032 2.07569 353.073 294.754 -1 4470327 15 1.58612e+09 5.57186e+08 1.08358e+09 21986.5 321.00 457.912 387.485 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.5.v common 12314.48 vpr 2.72 GiB -1 -1 444.57 1155000 6 6541.48 -1 -1 300412 -1 -1 3183 465 211 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 2847800 465 320 129393 107898 1 58474 4457 136 136 18496 dsp_top auto 844.0 MiB 2964.39 907860 5063951 1987132 2921705 155114 2781.1 MiB 416.84 2.53 7.95731 -241324 -7.95731 7.95731 22.03 0.555623 0.473983 83.803 68.9832 -1 1216557 18 5.92627e+08 1.88417e+08 4.08527e+08 22087.3 77.72 115.317 96.1388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.6.v common 21858.65 vpr 2.98 GiB -1 -1 733.32 1937992 3 1085.26 -1 -1 521520 -1 -1 3399 605 406 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3128500 605 420 162048 138469 1 77337 5130 138 138 19044 dsp_top auto 1117.5 MiB 18099.45 1227614 6196630 2461232 3536309 199089 3055.2 MiB 493.93 4.08 6.60155 -276231 -6.60155 6.60155 22.53 0.699439 0.597719 108.543 88.9515 -1 1702470 17 6.09712e+08 2.26871e+08 4.20597e+08 22085.5 125.59 156.881 130.869 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.7.v common 18763.57 vpr 3.15 GiB -1 -1 819.91 3196296 6 7366.29 -1 -1 557292 -1 -1 4950 354 492 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3303040 354 144 205704 176496 1 87942 6243 138 138 19044 dsp_top auto 1405.3 MiB 7794.25 1515088 7476043 3099214 4331878 44951 3225.6 MiB 827.52 5.11 7.55948 -381034 -7.55948 7.55948 25.21 1.0607 0.89608 155.442 127.043 -1 1992622 16 6.09712e+08 2.82751e+08 4.20597e+08 22085.5 161.80 213.877 177.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml proxy.8.v common 13318.28 vpr 3.27 GiB -1 -1 843.59 1554284 6 6540.38 -1 -1 358540 -1 -1 3057 346 235 -1 success 909f29c-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-08T17:55:38 mustang /homes/vtr-verilog-to-routing 3432868 346 656 128390 107845 1 57554 4662 152 152 23104 dsp_top auto 871.1 MiB 2767.71 935474 5766154 2271375 3256584 238195 3352.4 MiB 503.10 3.17 7.72231 -217179 -7.72231 7.72231 35.21 0.741053 0.636728 114.675 96.268 -1 1262212 17 7.41832e+08 2.11044e+08 5.09338e+08 22045.4 88.85 150.569 127.819 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/config.txt new file mode 100644 index 00000000000..34a11de6f9c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/config.txt @@ -0,0 +1,40 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/system_verilog/koios_sv + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Directory containing the verilog includes file(s) +includes_dir=benchmarks/verilog/koios + +# Add circuits to list to sweep +circuit_list_add=deepfreeze.style1.sv +circuit_list_add=deepfreeze.style2.sv +circuit_list_add=deepfreeze.style3.sv + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Add include files to the list. +# Some benchmarks instantiate hard dsp and memory blocks +# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. +# The hard_block_include.v file +# defines this macros, thereby enabling instantiations of the hard blocks +include_list_add=hard_block_include.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 -parser system-verilog diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/golden_results.txt new file mode 100644 index 00000000000..fc36fc4b154 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style1.sv common 22714.73 vpr 4.09 GiB -1 -1 949.56 2651192 3 16835.50 -1 -1 1290132 -1 -1 12293 27 396 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 4288252 27 513 420409 319910 1 173122 13274 122 122 14884 clb auto 2706.3 MiB 2229.92 358719 32218159 15492330 11108513 5617316 3575.6 MiB 1036.24 4.96 4.77742 -203483 -4.77742 4.77742 16.43 1.44734 1.24291 322.276 265.06 -1 525106 18 4.7523e+08 4.08959e+08 3.28149e+08 22047.1 89.42 403.175 333.904 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style2.sv common 24680.43 vpr 14.80 GiB -1 -1 827.06 2325884 3 11919.13 -1 -1 1064952 -1 -1 8475 6 140 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 15515036 6 513 281129 194945 1 142714 10896 338 338 114244 dsp_top auto 2163.1 MiB 2308.76 1873008 23434650 9090338 12891091 1453221 15151.4 MiB 1246.22 10.86 11.0869 -410426 -11.0869 11.0869 189.96 1.47102 1.33008 298.642 263.028 -1 2267430 14 3.68993e+09 7.02925e+08 2.50989e+09 21969.6 104.21 368.851 326.754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style3.sv common 9459.64 parmys 2.59 GiB -1 -1 1046.45 2716236 3 5554.19 -1 -1 1151548 -1 -1 4951 27 115 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 2669896 27 513 162561 120322 1 71039 5820 120 120 14400 dsp_top auto 1254.2 MiB 874.69 253375 9948140 4723336 3618748 1606056 2607.3 MiB 379.75 1.99 5.71612 -91795.4 -5.71612 5.71612 14.90 0.558622 0.482091 114.978 97.3208 -1 365131 15 4.60155e+08 2.08293e+08 3.17281e+08 22033.4 34.50 143.778 122.884 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/config.txt new file mode 100644 index 00000000000..2845596eb55 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/config.txt @@ -0,0 +1,33 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/system_verilog/koios_deepfreeze + +# Path to directory of architectures to use +archs_dir=arch/COFFE_22nm + +# Add circuits to list to sweep. +# Some of these benchmarks are designs with hard dsp and ram blocks +# but in this task, we're running them without enabling these +# blocks (that is, the macro `complex_dsp` and `hard_mem` are not defined). +circuit_list_add=deepfreeze.style1.sv +circuit_list_add=deepfreeze.style2.sv +circuit_list_add=deepfreeze.style3.sv + +# Add architectures to list to sweep +arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 -parser system-verilog diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/golden_results.txt new file mode 100644 index 00000000000..632cbdbdea6 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios_sv_no_hb/config/golden_results.txt @@ -0,0 +1,4 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style1.sv common 47967.94 vpr 10.31 GiB -1 -1 1750.70 3477528 3 33798.52 -1 -1 1967140 -1 -1 20253 27 1843 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 10811692 27 513 778797 600279 1 384107 23186 244 244 59536 memory auto 4968.5 MiB 3724.68 4867625 48601541 21188063 25604799 1808679 10366.4 MiB 3892.48 41.19 8.46401 -1.13947e+06 -8.46401 8.46401 82.35 2.83854 2.28574 443.492 355.56 -1 5791588 17 1.92066e+09 9.58441e+08 1.30834e+09 21975.7 419.89 594.451 484.887 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style2.sv common 48524.73 vpr 8.29 GiB -1 -1 1440.31 3118316 3 35219.69 -1 -1 1725016 -1 -1 22674 27 1231 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 8696204 27 513 757966 564979 1 371413 24999 196 196 38416 memory auto 4726.6 MiB 2712.89 5184470 52271336 22299033 27769653 2202650 7642.4 MiB 5209.27 55.51 9.75062 -937734 -9.75062 9.75062 50.02 2.30465 1.94566 366.253 293.69 -1 6516523 17 1.23531e+09 9.4276e+08 8.45266e+08 22003.0 925.98 493.024 402.412 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml deepfreeze.style3.sv common 41631.02 vpr 15.22 GiB -1 -1 1622.97 3431784 3 24896.76 -1 -1 1856148 -1 -1 20779 27 3333 -1 success 377bca3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.4.0-148-generic x86_64 2023-12-13T17:58:15 mustang /homes/sv-deep 15958564 27 513 703297 547641 1 350325 24854 324 324 104976 memory auto 4656.9 MiB 3861.23 5201129 61655974 26414908 31818866 3422200 15584.5 MiB 3575.85 19.40 9.71561 -1.53645e+06 -9.71561 9.71561 179.24 2.62795 2.23108 484.893 395.834 -1 6173057 19 3.39753e+09 1.08992e+09 2.30538e+09 21961.0 377.21 640.096 530.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt index 9107b58902d..2051826f1ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/task_list.txt @@ -4,7 +4,11 @@ regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch regression_tests/vtr_reg_weekly/vpr_ispd -regression_tests/vtr_reg_weekly/koios_odin -regression_tests/vtr_reg_weekly/koios_no_hard_block_odin -regression_tests/vtr_reg_weekly/koios -regression_tests/vtr_reg_weekly/koios_no_hard_block +regression_tests/vtr_reg_weekly/koios_proxy +regression_tests/vtr_reg_weekly/koios_proxy_no_hb +regression_tests/vtr_reg_weekly/koios_large_odin +regression_tests/vtr_reg_weekly/koios_large_no_hb_odin +regression_tests/vtr_reg_weekly/koios_large +regression_tests/vtr_reg_weekly/koios_large_no_hb +regression_tests/vtr_reg_weekly/koios_sv +regression_tests/vtr_reg_weekly/koios_sv_no_hb