Hi! I'm Ardhish Patel, a third-year B.Tech student in Electronics and Communication Engineering at the Indian Institute of Information Technology (IIIT) Nagpur.
💡 Passionate about VLSI design, with a keen interest in the complete RTL to GDSII flow — from digital logic to physical layout.
🔧 Experienced in hands-on projects involving SystemVerilog, FPGA-based prototyping, and ASIC design methodologies.
🧪 Actively exploring hardware verification using UVM, with a focus on optimizing designs for performance, power, and area efficiency.
📘 Continuously building expertise in EDA tools, timing closure, floorplanning, and low-power design strategies to gain a deeper understanding of the chip design process.
🤖 Also enthusiastic about the intersection of VLSI and machine learning, working on signal processing projects, stress detection systems, and ML-driven analysis using Python, TensorFlow, and scikit-learn.
