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Fossee summer fellowship 2025 iC submission Partha Pratim Nath #387

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38d823c
SN54H87: 4 bit True/Compliment, Zero/One Elements
Parthapnath Jul 13, 2025
56489ab
MC1445: Gate Controlled Two Channel Input Wideband Amplifier
Parthapnath Jul 13, 2025
66a8329
TL811M: Dual Channel Differential Comparators with strobes
Parthapnath Jul 13, 2025
184383b
TL560C: Precision Level Detector
Parthapnath Jul 13, 2025
74e52d2
CD4037A: CMOS Triple AND/OR Bi-phase Pairs
Parthapnath Jul 13, 2025
c85b178
HEF4531B: 13 input Parity Checker/Generator
Parthapnath Jul 13, 2025
8517469
74HC58: Dual AND/OR
Parthapnath Jul 13, 2025
94d059a
SN74ALS679: 12 bit Address Comparator
Parthapnath Jul 13, 2025
936e1d1
eSim_Subckt_lib_file
Parthapnath Jul 13, 2025
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113 changes: 113 additions & 0 deletions library/SubcircuitLibrary/IC_74HC58/74HC58-cache.lib
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# PORT
#
DEF PORT U 0 40 Y Y 26 F N
F0 "U" 50 100 30 H V C CNN
F1 "PORT" 0 0 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
S -100 50 100 -50 0 1 0 N
X ~ 1 250 0 100 L 30 30 1 1 B
X ~ 2 250 0 100 L 30 30 2 1 B
X ~ 3 250 0 100 L 30 30 3 1 B
X ~ 4 250 0 100 L 30 30 4 1 B
X ~ 5 250 0 100 L 30 30 5 1 B
X ~ 6 250 0 100 L 30 30 6 1 B
X ~ 7 250 0 100 L 30 30 7 1 B
X ~ 8 250 0 100 L 30 30 8 1 B
X ~ 9 250 0 100 L 30 30 9 1 B
X ~ 10 250 0 100 L 30 30 10 1 B
X ~ 11 250 0 100 L 30 30 11 1 B
X ~ 12 250 0 100 L 30 30 12 1 B
X ~ 13 250 0 100 L 30 30 13 1 B
X ~ 14 250 0 100 L 30 30 14 1 B
X ~ 15 250 0 100 L 30 30 15 1 B
X ~ 16 250 0 100 L 30 30 16 1 B
X ~ 17 250 0 100 L 30 30 17 1 B
X ~ 18 250 0 100 L 30 30 18 1 B
X ~ 19 250 0 100 L 30 30 19 1 B
X ~ 20 250 0 100 L 30 30 20 1 B
X ~ 21 250 0 100 L 30 30 21 1 B
X ~ 22 250 0 100 L 30 30 22 1 B
X ~ 23 250 0 100 L 30 30 23 1 B
X ~ 24 250 0 100 L 30 30 24 1 B
X ~ 25 250 0 100 L 30 30 25 1 B
X ~ 26 250 0 100 L 30 30 26 1 B
ENDDRAW
ENDDEF
#
# d_inverter
#
DEF d_inverter U 0 40 Y Y 1 F N
F0 "U" 0 -100 60 H V C CNN
F1 "d_inverter" 0 150 60 H V C CNN
F2 "" 50 -50 60 H V C CNN
F3 "" 50 -50 60 H V C CNN
DRAW
P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
X ~ 1 -300 0 200 R 50 50 1 1 I
X ~ 2 300 0 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# d_nand
#
DEF d_nand U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "d_nand" 50 100 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
A 150 49 100 6 900 0 1 0 N 250 50 150 150
P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
X IN1 1 -450 100 200 R 50 50 1 1 I
X IN2 2 -450 0 200 R 50 50 1 1 I
X OUT 3 450 50 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# d_nor
#
DEF d_nor U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "d_nor" 50 100 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
A -25 -124 325 574 323 0 1 0 N 150 150 250 50
A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
P 2 0 1 0 -250 -50 150 -50 N
P 2 0 1 0 -250 150 150 150 N
X IN1 1 -450 100 215 R 50 50 1 1 I
X IN2 2 -450 0 215 R 50 50 1 1 I
X OUT 3 450 50 200 L 50 50 1 1 O I
ENDDRAW
ENDDEF
#
# d_or
#
DEF d_or U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "d_or" 0 100 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
A -25 -124 325 574 323 0 1 0 N 150 150 250 50
A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
P 2 0 1 0 -250 -50 150 -50 N
P 2 0 1 0 -250 150 150 150 N
X IN1 1 -450 100 215 R 50 50 1 1 I
X IN2 2 -450 0 215 R 50 50 1 1 I
X OUT 3 450 50 200 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
#End Library
30 changes: 30 additions & 0 deletions library/SubcircuitLibrary/IC_74HC58/74HC58.cir
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* E:\FOSSEE\eSim\library\SubcircuitLibrary\74HC58\74HC58.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 07/01/25 12:06:33

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U2 Net-_U1-Pad3_ Net-_U16-Pad1_ d_inverter
U3 Net-_U1-Pad4_ Net-_U16-Pad2_ d_inverter
U4 Net-_U1-Pad5_ Net-_U17-Pad2_ d_inverter
U5 Net-_U1-Pad6_ Net-_U10-Pad1_ d_inverter
U6 Net-_U1-Pad7_ Net-_U10-Pad2_ d_inverter
U7 Net-_U1-Pad8_ Net-_U18-Pad2_ d_inverter
U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor
U14 Net-_U12-Pad3_ Net-_U1-Pad11_ d_inverter
U8 Net-_U1-Pad9_ Net-_U1-Pad1_ Net-_U11-Pad1_ d_nand
U9 Net-_U1-Pad10_ Net-_U1-Pad2_ Net-_U11-Pad2_ d_nand
U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand
U13 Net-_U11-Pad3_ Net-_U13-Pad2_ d_inverter
U15 Net-_U13-Pad2_ Net-_U1-Pad12_ d_inverter
U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT
U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_or
U17 Net-_U16-Pad3_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_or
U19 Net-_U17-Pad3_ Net-_U12-Pad1_ d_inverter
U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or
U18 Net-_U10-Pad3_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_or
U20 Net-_U18-Pad3_ Net-_U12-Pad2_ d_inverter

.end
88 changes: 88 additions & 0 deletions library/SubcircuitLibrary/IC_74HC58/74HC58.cir.out
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* e:\fossee\esim\library\subcircuitlibrary\74hc58\74hc58.cir

* u2 net-_u1-pad3_ net-_u16-pad1_ d_inverter
* u3 net-_u1-pad4_ net-_u16-pad2_ d_inverter
* u4 net-_u1-pad5_ net-_u17-pad2_ d_inverter
* u5 net-_u1-pad6_ net-_u10-pad1_ d_inverter
* u6 net-_u1-pad7_ net-_u10-pad2_ d_inverter
* u7 net-_u1-pad8_ net-_u18-pad2_ d_inverter
* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
* u14 net-_u12-pad3_ net-_u1-pad11_ d_inverter
* u8 net-_u1-pad9_ net-_u1-pad1_ net-_u11-pad1_ d_nand
* u9 net-_u1-pad10_ net-_u1-pad2_ net-_u11-pad2_ d_nand
* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
* u13 net-_u11-pad3_ net-_u13-pad2_ d_inverter
* u15 net-_u13-pad2_ net-_u1-pad12_ d_inverter
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_or
* u17 net-_u16-pad3_ net-_u17-pad2_ net-_u17-pad3_ d_or
* u19 net-_u17-pad3_ net-_u12-pad1_ d_inverter
* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
* u18 net-_u10-pad3_ net-_u18-pad2_ net-_u18-pad3_ d_or
* u20 net-_u18-pad3_ net-_u12-pad2_ d_inverter
a1 net-_u1-pad3_ net-_u16-pad1_ u2
a2 net-_u1-pad4_ net-_u16-pad2_ u3
a3 net-_u1-pad5_ net-_u17-pad2_ u4
a4 net-_u1-pad6_ net-_u10-pad1_ u5
a5 net-_u1-pad7_ net-_u10-pad2_ u6
a6 net-_u1-pad8_ net-_u18-pad2_ u7
a7 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
a8 net-_u12-pad3_ net-_u1-pad11_ u14
a9 [net-_u1-pad9_ net-_u1-pad1_ ] net-_u11-pad1_ u8
a10 [net-_u1-pad10_ net-_u1-pad2_ ] net-_u11-pad2_ u9
a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
a12 net-_u11-pad3_ net-_u13-pad2_ u13
a13 net-_u13-pad2_ net-_u1-pad12_ u15
a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
a15 [net-_u16-pad3_ net-_u17-pad2_ ] net-_u17-pad3_ u17
a16 net-_u17-pad3_ net-_u12-pad1_ u19
a17 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
a18 [net-_u10-pad3_ net-_u18-pad2_ ] net-_u18-pad3_ u18
a19 net-_u18-pad3_ net-_u12-pad2_ u20
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
73 changes: 73 additions & 0 deletions library/SubcircuitLibrary/IC_74HC58/74HC58.pro
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=adc-dac
LibName2=memory
LibName3=xilinx
LibName4=microcontrollers
LibName5=dsp
LibName6=microchip
LibName7=analog_switches
LibName8=motorola
LibName9=texas
LibName10=intel
LibName11=audio
LibName12=interface
LibName13=digital-audio
LibName14=philips
LibName15=display
LibName16=cypress
LibName17=siliconi
LibName18=opto
LibName19=atmel
LibName20=contrib
LibName21=power
LibName22=eSim_Plot
LibName23=transistors
LibName24=conn
LibName25=eSim_User
LibName26=regul
LibName27=74xx
LibName28=cmos4000
LibName29=eSim_Analog
LibName30=eSim_Devices
LibName31=eSim_Digital
LibName32=eSim_Hybrid
LibName33=eSim_Miscellaneous
LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
LibName37=eSim_Nghdl
LibName38=eSim_Ngveri
LibName39=eSim_SKY130
LibName40=eSim_SKY130_Subckts
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