Vending Controller FPGA Project

Overview

This project implements a simple vending machine controller as a finite state machine (FSM) in Verilog.
It accepts coins (5¢, 10¢, 25¢) and dispenses an item priced at 40¢, managing balance and returning change.

Designed for the Basys 3 FPGA board (Artix-7 xc7a35tcpg236-1).

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Features

• Accepts coins: 5, 10, and 25 cents.
• Tracks inserted balance.
• Dispenses product once 40¢ is reached or exceeded.
• Returns correct change for overpayment.
• Finite State Machine with four states:
  • IDLE
  • ACCUMULATE
  • DISPENSE
  • RETURN

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Module Interface

Inputs

• clk — system clock
• reset — synchronous reset signal
• coin_5 — input for 5¢ coin insertion
• coin_10 — input for 10¢ coin insertion
• coin_25 — input for 25¢ coin insertion

Outputs

• dispense — signals when to dispense the product
• return_change — 8-bit value indicating change to return
• state — current FSM state (for debugging)
• balance — current accumulated balance (for debugging)

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Testbench

Included tb_vending_controller.v simulates various coin insertion scenarios, including exact payment and overpayment, verifying the controller behavior.

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Files

• vending_controller.v — main vending machine controller module
• tb_vending_controller.v — testbench for simulation
• README.md — this documentation

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Author

Maxim Pintea