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Re-design Dispatch Sink to communicate more sparsely

enhancementNew feature or requestNew feature or request

rtlRegister Transfer Level hardware designRegister Transfer Level hardware design

Status: Open.

#49 In TENNLab-UTK/fpga;

· keegandent opened on Jan 10, 2025

Stream Source CLR Packet Clobbers Spike Data

bugSomething isn't workingSomething isn't working

defer/delayImpeded or irrelevant due to other issueImpeded or irrelevant due to other issue

Status: Open.

#48 In TENNLab-UTK/fpga;

· BGull00 opened on Jan 9, 2025

Remove references to Intel

documentationImprovements or additions to documentationImprovements or additions to documentation

good first issueGood for newcomersGood for newcomers

Status: Open.

#45 In TENNLab-UTK/fpga;

· keegandent opened on Jan 8, 2025

Testing CI

enhancementNew feature or requestNew feature or request

Status: Open.

#35 In TENNLab-UTK/fpga;

· keegandent opened on Sep 12, 2024

Networks and Input Spike Rasters for Integration Testing

frameworkTENNLAB Framework interoperability or API complianceTENNLAB Framework interoperability or API compliance

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#34 In TENNLab-UTK/fpga;

· keegandent opened on Sep 12, 2024

Neurons without incoming synapses that are on a path from an input neuron are handled erroneously in hardware

bugSomething isn't workingSomething isn't working

defer/delayImpeded or irrelevant due to other issueImpeded or irrelevant due to other issue

rtlRegister Transfer Level hardware designRegister Transfer Level hardware design

Status: Open.

#33 In TENNLab-UTK/fpga;

· BGull00 opened on Sep 12, 2024

Multiple Networks on Processor

defer/delayImpeded or irrelevant due to other issueImpeded or irrelevant due to other issue

frameworkTENNLAB Framework interoperability or API complianceTENNLAB Framework interoperability or API compliance

rtlRegister Transfer Level hardware designRegister Transfer Level hardware design

Status: Open.

#9 In TENNLab-UTK/fpga;

· keegandent opened on Jul 29, 2024

"Binary" or "Fire" Source Modes

enhancementNew feature or requestNew feature or request

rtlRegister Transfer Level hardware designRegister Transfer Level hardware design

Status: Open.

#8 In TENNLab-UTK/fpga;

· keegandent opened on Jul 29, 2024

Create distinction between targets and build hosts

enhancementNew feature or requestNew feature or request

Status: Open.

#2 In TENNLab-UTK/fpga;

· keegandent opened on Jul 1, 2024