add sw_testbench #50
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add sw_testbench #50
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add sw testbench; add FF between RF and ALU
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| always @(posedge clk) begin | ||
| dataA <= rd1; | ||
| dataB <= rd2; | ||
| end |
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So i think figured out what was the issue with the sw -- it was not really related to the PC using the single clock cycle stuff; the real problem was that the dataA and dataB registers here, because they technically already existed in the RF implementation (i.e. the reads were "clocked"); so this was adding another clock cycle basically.
Both approaches are correct, but i think your implementation is probably more inline with how the diagram is layed out -- the sync register is outside of RF and the reads are combinational ; i pushed the update to your PR along with the test bench fixes and it should be good to go now
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add sw testbench; add FF between RF and ALU