0.21

What's Changed

• Bump Yosys version to 0.54 by @yrabbit in #349
• Add forgotten wires to IO registers by @yrabbit in #350
• Remove the current setting for True LVDS. by @yrabbit in #352
• Put back the wires with partial fuses. by @yrabbit in #351
• Bump the Yosys version. by @yrabbit in #356

Full Changelog: 0.20...0.21

0.20

What's Changed

• BUGFIX. Use correct IDE files. by @yrabbit in #334
• Use unspecified attributes for CLKDIV/CLKDIV2 by @yrabbit in #336
• Remove a non-existent module from setup. by @yrabbit in #338
• Remove ByteString usages by @xtexx in #340
• Remove bitstream templates. by @yrabbit in #339
• Use a special case of the histogram. by @yrabbit in #341
• update dockerfile by @pepijndevos in #343
• automatically push docker image to docker hub by @pepijndevos in #344
• work around license server issues by @pepijndevos in #346
• Add Module for Tracing Signals by @Seyviour in #303
• Remove extra file. by @yrabbit in #347
• Don't compress EMCU examples. by @yrabbit in #348
• New ide 191003 by @yrabbit in #345

New Contributors

• @xtexx made their first contribution in #340

Full Changelog: 0.19...0.20

Technical release

What's Changed

• Bump the yosys version by @yrabbit in #325
• Eanble segments associated with spines 6 and 7. by @yrabbit in #326
• Add BANK_VCCIO attribute processing. by @yrabbit in #327
• Add BSRAM operation check by @yrabbit in #328
• Defining IO parameters in the examples by @yrabbit in #329
• Bump the Yosys version. by @yrabbit in #330
• Timing calculation by @yrabbit in #331
• Add HCLK delays information. by @yrabbit in #333
• Fixed bitstream compression, tested on tangnano 9k hardware by @regymm in #324

New Contributors

• @regymm made their first contribution in #324

Full Changelog: 0.18...0.19

0.18

What's Changed

• Use nextpnr 0.8 by @yrabbit in #319
• Remove legacy chip databases by @yrabbit in #320
• Fix PLL parameter generation script by @yrabbit in #323

Full Changelog: 0.17...0.18

0.17

What's Changed

• Add HCLK wires to PLL. by @yrabbit in #317
• Add segmented clock wires. by @yrabbit in #314
• Implement the DLLDLY primitive. by @yrabbit in #318

Full Changelog: 0.16...0.17

0.16

What's Changed

• Fix another gowin_unpack mistype. by @yrabbit in #285
• Use USB-C UART on Tangnano20k by @yrabbit in #287
• add missing examples to makefile by @pepijndevos in #290
• Fix PLL limits for GW2A-18 C8/I7 by @TrAyZeN in #293
• Fix pll codegen range limit comments by @TrAyZeN in #292
• WIP: Add family footnote to 20k-boards by @TheZoq2 in #296
• Adapt the examples to the latest Yosys by @yrabbit in #297
• Add IEM (Input Edge Monitor) by @yrabbit in #291
• Add IODELAY. by @yrabbit in #295
• Restore CUPCDN with a different bit pattern by @aerkiaga in #301
• Implement FF in IO blocks. by @yrabbit in #298
• Document the MIPI specifics by @yrabbit in #305
• out of tree build by @pepijndevos in #307
• Implement MIPI and I3C primitives by @yrabbit in #306
• Remove examples that use gowin-nextpnr. by @yrabbit in #308
• gowin_pack: fix invalid escape sequence by @whitequark in #304
• LW doc by @yrabbit in #310
• Fix examples in CI by @yrabbit in #313
• Unpack a DFFs with separated inputs from LUTs. by @yrabbit in #311
• Fix the CLKDIV examples. by @yrabbit in #315
• Implement CLKDIV2 and CLKDIV for all boards. by @yrabbit in #316

New Contributors

• @TrAyZeN made their first contribution in #293
• @TheZoq2 made their first contribution in #296
• @aerkiaga made their first contribution in #301

Full Changelog: 0.15...0.16

0.15

What's Changed

• add magic sdram pin constraints by @pepijndevos in #280
• Implement EMCU primitive by @yrabbit in #279
• Fix mistype. by @yrabbit in #283

Full Changelog: 0.14...0.15

0.14

What's Changed

• Assign missing time delays by @yrabbit in #272
• BUGFIX. Fix dat offset. by @yrabbit in #274
• Remove the magic numbers by @yrabbit in #275
• Use builtin USB-serial by @yrabbit in #276
• Implement the UserFlash primitives. by @yrabbit in #277
• Add DHCEN primitive. by @yrabbit in #261

Full Changelog: 0.13...0.14

0.13

What's Changed

• Add PLL pads. by @yrabbit in #241
• Doc. Brief notes on DSP operation by @yrabbit in #246
• Fix CI by @yrabbit in #248
• BUGFIX. Fix BSRAM unpacking. by @yrabbit in #247
• Add description of BSRAM harness by @yrabbit in #249
• Fix IO unpack by @yrabbit in #250
• Describe the BSRAM regs in GW1NR-9C and GW2AR-18C by @yrabbit in #251
• BSRAM. Corrective action. by @yrabbit in #252
• BSRAM BLKSEL fix by @yrabbit in #254
• Clarification in the doc about BSRAM BLKSEL by @yrabbit in #255
• Relax BSRAM initialization data requirements by @yrabbit in #253
• Fix regex by @max-kudinov in #259
• Fix pROM(X9). by @yrabbit in #256
• Implement power saving primitive BANDGAP by @yrabbit in #257
• Fix bits to bytes conversion. by @yrabbit in #265
• Add wire class info by @yrabbit in #266
• Add dynamic clock control by @yrabbit in #260
• HCLK Support by @Seyviour in #258
• HCLK. Primary clock pins by @yrabbit in #263
• Add delays for primary clocks. by @yrabbit in #270

New Contributors

• @max-kudinov made their first contribution in #259

Full Changelog: 0.12...0.13

0.12

What's Changed

• Add examples with tiny RISCV by @yrabbit in #236
• Add Functions for Concise Tile Parsing by @Seyviour in #237
• update yosys CI branches by @pepijndevos in #238
• Implement the DSP primitive. by @yrabbit in #239

Full Changelog: 0.11.1...0.12