Copy O-RAN 6.12 series from oran-linux repo

.gitignore

@@ -177,3 +177,7 @@ sphinx_*/
 
 # Rust analyzer configuration
 /rust-project.json
+
+# Yocto symlinks
+oe-logs
+oe-workdir

Documentation/devicetree/bindings/dma/adi-dma.txt

@@ -0,0 +1,113 @@
+* Analog Devices Direct Memory Access (DMA) Controller for ADRV906X-series processors
+
+This document will only describe differences to the generic DMA Controller and
+DMA request bindings as described in dma/dma.txt
+
+* DMA controller
+
+Required properties:
+- compatible : Should be "adi,mdma-controller" or "adi,dma-controller".
+- reg : Should contain DMA registers location and length
+- #dma-cells : Has to be 1. Does not support anything else.
+- interrupts : subnode, containing:
+    adi,id:
+    adi,src-offset: Offset from base address
+    adi,skip-interrupts: Set to 0 usually.  Setting to 1 will skip handling interrupts,
+                         so the SHARC cores may handle them instead.
+    interrupts: list of interrupts, from processor's GIC interrupt list
+    interrupt-names: list of interrupt names
+Optional properties:
+- dde-descriptor-mode : this is optionally specified for a dma channel. A dma channel with this
+                        property runs in descriptor list mode. otherwise the dma channel 
+                        runs in register based mode.
+- dde-sync-bit-disable: disable the DDE sync bit for a dma channel. A sync bit is used to synchronize
+                        work unit transitions.
+
+Example (DMA):
+
+    sport0_dma_cluster: dma@0x31022000 {
+            compatible = "adi,dma-controller";
+            reg = <0x31022000 0x1000>;
+            status = "okay";
+            #dma-cells = <1>;
+
+            sport0a: channel@0 {
+                    adi,id = <0>;
+                    adi,src-offset = <0>;
+                    adi,skip-interrupts = <0>;
+                    interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+                    interrupt-names = "complete", "error";
+            };
+
+            sport0b: channel@1 {
+                    adi,id = <1>;
+                    adi,src-offset = <0x80>;
+                    adi,skip-interrupts = <0>;
+                    interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+                    interrupt-names = "complete", "error";
+            };
+    };
+
+Example (MDMA):
+
+    mdma: dma@0x3109a000 {
+            compatible = "adi,mdma-controller";
+            reg = <0x3109a000 0x1000>;
+            status = "okay";
+
+            sdma2: channel@40 {
+                    adi,id = <40>;
+                    // The destination interrupts are used for primary complete detection
+                    interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+                    interrupt-names = "complete", "error", "complete2", "error2";
+                    adi,src-offset = <0>;
+                    adi,dest-offset = <0x80>;
+            };
+    };
+
+* DMA client
+
+Clients have to specify the DMA requests with phandles in a list.
+
+Required properties:
+- dmas: List of one or more DMA request specifiers. One DMA request specifier
+    consists of a phandle to the DMA controller followed by the integer
+    specifying the request line.
+- dma-names: List of string identifiers for the DMA requests. For the correct
+    names, have a look at the specific client driver.
+
+Example:
+
+    i2s0: i2s0@0 {
+            ...
+            dmas = <&sport0_dma_cluster 0>, <&sport0_dma_cluster 1>;
+            dma-names = "tx", "rx";
+            ...
+    };
+
+From a driver level, additional configuration of things like bus width can set via:
+
+    dma_config.direction = DMA_DEV_TO_MEM;
+    dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+    dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+    dma_config.src_maxburst = 1;
+    dma_config.dst_maxburst = 1;
+
+    dmaengine_slave_config(crc->dma_ch, &dma_config);
+
+Or cyclic mode can be enabled via something like:
+    (a cyclic descriptor will reuse itself, triggering callbacks as expected, * and will not free itself when it finishes)
+
+    desc = dmaengine_prep_dma_cyclic(uart->rx_dma_channel, uart->rx_dma_phy,
+        UART_XMIT_SIZE, DMA_RX_XCOUNT, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
+    desc->callback = adi_uart4_serial_dma_rx;
+    desc->callback_param = uart;
+
+MDMA controllers can be found automatically through the kernel's standard DMA memcpy API:
+
+    struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);

Documentation/devicetree/bindings/gpio/gpio-adi-adrv906x.txt

@@ -0,0 +1,21 @@
+Analog Device Inc. ADRV906x SoC GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "adi,adrv906x-gpio".
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- #gpio-cells: Should be two. For consumer use see gpio.txt.
+- ngpios: Number of GPIO lines (0..n-1)
+- gpio-controller: Specifies that the node is a gpio controller.
+- pintmux: Specifies the base address for the pin interrupt mux associated with the GPIO controller
+
+Example:
+
+    gpio1: gpio@2021B000 {
+        compatible = "adi,adrv906x-gpio";
+        reg = <0x2021B000 0x1000>;
+        pintmux = <0x20102200>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        ngpios = <ADI_ADRV906X_PIN_COUNT>;
+    }; 

Documentation/devicetree/bindings/i2c/adi,twi.yaml

@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/adi,twi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices Inter IC (I2C) controller
+
+maintainers:
+  - Slawomir Kulig <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - adi,twi
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-khz:
+    description: Desired I2C bus clock frequency in kHz. If not specified,
+                 frequency defined by CONFIG_I2C_ADI_TWI_CLK_KHZ will be
+                 used (default 50 kHz).
+                 If timing parameters match, the bus clock frequency can
+                 be from 21 to 400 kHz.
+    default: 50
+    minimum: 21
+    maximum: 400
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - interrupts
+  - clock-khz
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #define I2C_0_BASE          0x20760000
+    #define I2C_IRQ_S2F_PIPED_0 149
+
+    i2c0: twi@I2C_0_BASE_UADDR {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "adi,twi";
+        reg = <I2C_0_BASE 0xFF>;
+        interrupts = <GIC_SPI I2C_IRQ_S2F_PIPED_0 IRQ_TYPE_LEVEL_HIGH>;
+        clock-khz = <100>;
+        clocks = <&sysclk>;
+        status = "disabled";
+    };

Documentation/devicetree/bindings/iio/dac/adi,pwm-dac.yaml

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,pwm-dac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices PWM DAC
+
+maintainers:
+  - Jie Zhang <[email protected]>
+
+properties:
+  compatible:
+    const: adi,pwm-dac
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Clock phandle for input clock
+
+  adi,iovdd-microvolt:
+    description: |
+      The IOVDD voltagge [mV]
+    minimum: 0
+    maximum: 5000000
+
+  adi,gpio-max-frequency:
+    description: |
+      The maximum frequency of GPIO [Hz]
+    minimum: 0
+    maximum: 0xffffffff
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - adi,iovdd-microvolt
+  - adi,gpio-max-frequency
+
+examples:
+  - |
+    #define PWM_BASE  0x20727000
+    dac@PWM_BASE_UADDR {
+        compatible = "adi,pwm-dac";
+        reg = <PWM_BASE 0x100>;
+        clocks = <&hsdigclk>;
+        adi,iovdd-microvolt = <3300000>;
+        adi,gpio-max-frequency = <122880000>;
+    };
+...

Documentation/devicetree/bindings/misc/adi,tru.yaml

@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/adi,tru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices Trigger Routing Unit (TRU)
+
+maintainers:
+  - Jie Zhang <[email protected]>
+
+properties:
+  compatible:
+    const: adi,tru
+
+  reg:
+    maxItems: 1
+
+  adi,tru-last-source-id:
+    description: |
+      The last TRU trigger source ID
+    minimum: 0
+    maximum: 0xff
+
+  adi,tru-last-target-id:
+    description: |
+      The last TRU trigger target ID
+    minimum: 0
+    maximum: 0xffffffff
+
+  adi,tru-connections-preset:
+    description: |
+      Preset connections between TRU sources and targets
+
+  adi,tru-connections-preset-locked:
+    description: |
+      The preset connections between TRU sources and targets are locked.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - adi,tru-last-source-id
+  - adi,tru-last-target-id
+
+examples:
+  - |
+    #define TRU_BASE  0x20052000
+
+     tru0: tru@TRU_BASE_UADDR {
+       compatible = "adi,tru";
+       reg = <TRU_BASE 0x800>;
+       /* TODO replace 100 with actual last trigger source ID */
+       adi,tru-last-source-id = <100>;
+       adi,tru-last-target-id = <79>;
+       /* each connection is <source target> */
+       /*
+       adi,tru-connections-preset = <1 2>,
+                                    <25 32>,
+                                    <3 4>;
+       adi,tru-connections-preset-locked;
+       */
+     };
+...