This GitHub repository documents the Semiconductor Packaging - Fundamentals of Design and Testing 10-days Workshop offered by VSD Corp. Pvt. Ltd. attended from 9-20 May, 2025.
The workshop offers a full-pipeline understanding of the semiconductor packaging process, starting from the fundamentals and evolution of packaging to advanced 2.5D/3D architectures. We gain insights into advanced interconnect technologies, RDLs & interposers, assembly processes, package reliability analysis, and also get to perform hands-on thermal simulations, package design and modeling using ANSYS tools.
Table of Contents
| Module # | Topic(s) Covered | Status |
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| Mod. 1 | Packaging Evolution: From Basics to 3D Integration
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| Mod. 2 | From Wafer to Package: Assembly and Manufacturing Essentials |
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| Mod. 3 | Labs: Thermal Simulation of Semiconductor Packages with ANSYS |
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| Mod. 4 | Ensuring Package Reliability: Testing and Performance Validation |
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| Mod. 5 | Package Design and Modeling: Building a Semiconductor Package from Scratch |
Semiconductor packaging refers to the final stage of semiconductor device fabrication, where the finished semiconductor die is enclosed in a protective package that allows it to be integrated into electronic systems. Basically, the package helps transition a fragile silicon die fabricated in a foundry cleanroom into the real-world system/ product.
The key Functions of semiconductor package are:
- Protection from external environmental (physical/ mechanical damage, humidity, corrosion/ contaminants & chemical damage and ESD)
- Electrical connectivity between the die and the external environment via leads (pins, balls or lands)
- Mechanical support and connection of the die to the system
- Thermal dissipation to conduct heat away from the die
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The semiconductor manufacturing process consists of the front-end process which refers to the wafer manufacturing and the back-end process which consists of packaging and testing. (Even the wafer manufacturing process is split into a front-end and back-end process - with the front-end typically consisting of the CMOS-making process, and the back-end comprising the metal wiring formation process that comes after the CMOS is made.)
The following figure is a flow chart that shows the relationship between the semiconductor manufacturing process and the semiconductor industry. The first phase of the packaging and testing process is wafer testing. Afterwards, packages are made in the packaging process and followed by the package test stage.
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Ref: SK Hynix Newsroom: Semiconductor Back-End Process Episode 3
- Companies like Nvidia, Qualcomm and Apple that only design semiconductors are called “fabless.”
- Products designed by fabless companies are made into wafers, and the facilities that produce these wafers are called “foundries.” Global companies with these facilities include TSMC, Global Foundries and UMC.
- Then, there are companies that test and package products that were designed by fabless vendors and, later, made into wafers at foundries. These are called OSAT (Out-Sourced Assembly and Test) which include companies such as ASE and Amkor.
- Finally, there are the companies that do everything from design, wafer production, and packaging, to testing. These companies are called IDMs (Integrated Device Manufacturer).
Selecting the right semiconductor package is a critical step in electronic system design, as it affects performance, cost, thermal management, size, and reliability.
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The criteria for semiconductor package selection generally fall into the following key categories:
- Application-specific Requirements
- Logic/ Memory die
- Power semiconductor die)
- Electrical Requirements
- I/O Pin Count
- Signal Integrity for high speed I/Os
- Power Delivery
- Thermal Requirements
- Thermal Dissipation
- Operating Temperature Range
- Mechanical and Physical constraints
- Form Factor: Footprint and chip height requirements for the system
- System Integration needs: MCM, SiP, 2.5/3D packaging for tighter integration
- Cost Considerations
- Package cost
- Board/ System Assembly cost
- Reliability and Durability
- Mechanical stress
- Thermal cycling
- Moisture and other environmental factors
The following figure below shows the structure of a typical chip package and the connection hierarchy:
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A typical IC package consists of:
- Die: The semiconductor die itself.
- Carrier/ Substrate: The carrier or substrate is the intermediate structure on which the die sits and provides both mechanical support and electrical contact.
- Die-to-carrier interconnections: The die is connected to the substrate using bond wires or solder bumps
- Carrier-to-Board interconnections: The substrate is often soldered/ connected to the PCB for integration into larger systems using pins, leads balls or lands.
- Mold Compound: A molding compound (commonly epoxy or plastic) encapsulates the whole die & other components, and provides protection from moisture, contaminants, and physical damage.
Mounting Technologies:
- Through-hole Mounting
- TO : Transistor Outline
- SIP : Single In-line Package
- DIP : Dual In-line Package
- PGA : Pin Grid Array
- Surface Mount Technology:
- (T)SOT : (Thin) Small Outline Transistor
- (T)SOP : (Thin) Small Outline Package
- SOIC : Small Outline IC Package
- QFN : Quad Flat No-leads
- QFP : Quad Flat Package
- PBGA : Plastic Ball Grid Array
- LGA : Land Grid Array
- FCBGA : Flip Chip Ball Grid Array
- CSP : Chip Scale Package
- Advanced Packages
- PoP : Package on Package (Qualcomm SD series, Apple A-Series, Samsung Exynos etc.)
- MCM : Multi-Chip Module (eg: Intel Broadwell)
- SiP : System-in-Package (Apple S1)
- CoWoS : Chip on Wafer on Substrate (eg: Nvidia GP100, GV100, GA100, etc.)
The various types of semiconductor packages can be broadly grouped into two main categories:
- Conventional Packages
- Wafer-level packages
In conventional packaging, the wafer is sawed into dice before the chip is packaged, while wafer-level packaging involves a part, or all, of the packaging process being performed at the wafer level before proceeding with wafer sawing.
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| Ref: SK Hynix Newsroom: Semiconductor Back-End Process Episode 3_ |
Depending on the medium of the package, packages can be further categorized into leadframe and laminate packages.
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Leadframe-Based Packages
- DIP: Traditional, with wirebonds and external leads
- QFN: Compact with exposed thermal pads
- Leadframe CSP & QFP: Scaled for density and SMT
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Laminate-Based Packages
- PBGA: Wirebonded to laminated substrates
- Flip Chip PBGA: Superior signal and thermal performance
- LGA, FCCSP: Common in modern devices
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Advanced Substrates
- 2D: Dies placed side-by-side on the same substrate
- 2.1D: Adds RDL for better routing
- 2.3D: Uses organic interposers
- 2.5D: Silicon interposer for high-speed interconnects (e.g.: CoWoS)
The below figure shows the anatomy of some of the commonly used leadframe and laminate based packages and advanced substrates:
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RDL (Redistribution Layer) is a metal layer added on top of a die or wafer to reroute the I/O pads to new locations. This enables more flexible bump layouts, especially important for fan-out packages or wafer-level chip scale packaging (WLCSP).
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Applications
- Fan-out wafer-level packaging (FO-WLP, FO-BGA)
- Panel-level packaging (PLP)
- Multi-die integration
- System-in-Package (SiP)
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Advantages:
- Allows larger bump pitch for finer pad layouts
- Reduces package size and thickness
- Enables multi-chip placement and interconnect on a single substrate
An interposer is a passive or active layer inserted between the die and the substrate, acting as an intermediate routing interface. It enables dense signal routing, power delivery, and die-to-die interconnect.
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Types: Silicon, Organic, Glass
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Functions: - Routes signals between multiple dies (e.g., chiplets) - Provides thermal expansion management - Enables high bandwidth communication
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Passive vs. Active Interposers:
- Passive: No logic, just routing and vias
- Active: Includes power delivery, clocking, or even memory logic
- 2.5D: Multiple dies (e.g., CPU + HBM) placed side-by-side on a common interposer. Interposer provides connectivity, not the substrate directly. Popular in HPC and AI (e.g., AMD Instinct, NVIDIA GPUs with HBM).
- 3D: Dies are stacked vertically, interconnected through Through-Silicon Vias (TSVs). 3D NAND, HBM memory stacks, logic-on-logic stacking.
The following table provides a comparison of the various IC package types and their typical applications:
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Selecting the right semiconductor packaging depends on multiple criteria across performance, reliability, form factor and cost.
This section covers the semiconductor supply chain and provides a detailed look into a package manufacturing unit (ATMP – Assembly, Testing, Marking, and Packaging).
The semiconductor supply chain is a multi-step process that transforms raw silicon into fully functional electronic products. The major steps are:
| Semiconductor Supply Chain Review |
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1. Design : Chip design and verification
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2. Wafer Fabrication (Foundry) : Physical ICs are manufactured onto wafers using photolithography and other processes
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3. Packaging Assembly & Test : ICs are cut (diced), bonded, encapsulated, and tested
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4. Board Assembly & Test : Multiple packaged ICs are mounted and board-level validation
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5. System Integration & Distribution
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The ATMP process involves four core activities: Assembly, Testing, Marking, and Packaging. The ATMPs could be OSATs (like ASE, Amkor, TATA etc.) or in-house ATMPs of IDMs (like Intel, Samsung, Micron) or Foundries (like TSMC, Samsung Foundry)
Typical layout of an ATMP:  |
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- Material Preparation and Storage - Incoming Wafers, Substrates, Leadframes, Mold Compounds, Consumables
- Processing Zone (Clean Room: ISO Class 6 & 7)
- Major activities:
- Die Attach & Mount
- Wire or Flip-Chip Bonding
- RDL formation
- Encapsulation/ molding.
- Testing Area - Electrical Tests - Burn-in Test - Reliability chamber testing
- Warehouse - Storage of packaged ICs
This section explains the wafer preparation process inside an ISO Class 7 cleanroom of an ATMP (Assembly, Testing, Marking, and Packaging) facility.
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Incoming Wafer Carrier: Wafers arrive in a protective carrier that ensures they remain uncontaminated before entering the processing line.
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Wafer Inspection: The wafers are visually and optically inspected for surface defects, contamination, or damage before further processing.
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Wafer Front Tape Lamination: A protective tape is laminated on the front (device side) of the wafer to protect it during subsequent processes like grinding and dicing.
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Wafer Backside Grinding: The wafer’s backside is ground using a rotating grinding wheel to reduce the wafer thickness from the ~700um to around 200um and enable better thermal performance and flexibility for final packaging.
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Tape Frame Mounting to Wafer Backside: After grinding, the wafer is mounted on a ring frame using an adhesive tape. This stabilizes the wafer and keeps individual die in place during dicing.
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Two-step Wafer Dicing (Laser Grooving + Blade Dicing):
6.1 Laser Grooving: Precision laser cuts grooves along scribe lines to weaken the wafer structure.
6.2 Blade Dicing: A high-precision blade is then used to physically dice the wafer into individual dies or chips.
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Die Attach: The individual (die) is attached to a substrate or lead frame using epoxy.
1.1 The Epoxy is dispensed onto the die in some pattern so as to avoid any voids during attach. (Pattern complexity vs. speed of processing trade-off)
1.2 The die is picked up by the pick-up head, and
1.3 Placed on the Die Attach Film (DAF) -
Curing: The die-attached unit is subjected to a heating process to cure the epoxy, ensuring a strong and stable bond between the die and the substrate.
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Wire Bonding: Fine gold or aluminum wires are bonded between the die and the package substrate pads using thermal and ultrasonic energy.
3.1 Formation of a ball bond using an EFO (Electronic Flame-Off) spark 3.2 Bonding the ball to the die pad (using pressure, vibration, heat) 3.3 Creating a wire loop 3.4 Forming a crescent bond on the substrate side -
Molding (Transfer Molding): A mold compound is injected to encapsulate the wire-bonded die, providing protection from environmental damage and mechanical stress. Resin flows uniformly to cover the entire chip.
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Marking (Laser): Laser marking is used to engrave identification codes, logos, or batch numbers on the molded package surface.
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Singulation (Dicing Blade): The molded wafer is cut into individual units (ICs) using a dicing blade. A thinner blade is typically used to minimize chipping and maximize precision.
Flip chip packaging enhances electrical performance and I/O density by mounting the die face-down on the substrate.
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Bump Formation on Silicon (Si): 1.1 Solder bumps are created on the die.
1.2 The bumps are then reflowed to form strong electrical and mechanical connections. -
Chip Flip and Placement: 2.1 The chip is flipped upside down.
2.3 Flux is dispensed on to the substrate to aid solder wetting.
2.2 Solder balls are aligned with the substrate’s bond pads. -
Solder Reflow: The chip is heated so that the solder balls melt and bond with the substrate.
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Flux Cleansing: The excess residual flux is removed using solvent spray to prevent corrosion.
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Underfill Dispensing: Underfill material is applied to improve mechanical strength and thermal conductivity between the die and substrate.
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Underfill Cure: Heated to cure the underfill.
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Molding: A protective mold compound is applied.
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Marking: Laser marking is done for identification (part number, lot, batch, date of manufacture etc.) and traceability.
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Ball Mounting and Reflow: Solder balls are mounted on the substrate. A final reflow process ensures firm attachment of solder balls.
Wafer-Level Packaging (WLP) is a technique where the entire packaging process is done at the wafer level, before dicing and offers smaller size, and lower cost.
There are two main types of WLP:
- Fan-in WLP (FI-WLP) : I/O pads are redistributed within the die area to match the solder bumps.
- Fan-out WLP (FO-WLP) : Uses RDLs to extend the I/O pads beyond the die area, enabling higher I/O density.
FO-WLP Process
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Reconstitution Process: 1.1 Diced Wafer is taken
1.2 From this, only the known-good dies are picked and placed onto a temporary carrier.
1.3 Molding to form a single reconstituted wafer after releasing the carrier. -
RDL (Redistribution Layer) Preparation: 2.1 Dielectric & Metal are layers are deposited on to the reconstituted wafer and patterned.
2.2 Multiple such RDL layers are patterned to form the final RDL, similar to the metallization stages in FEOL/ CMOS facbrication -
Solder Ball Attach: Solder Balls are mounted on the final RDL pads to enable surface mounting.
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Final Laser Marking and Singulation: Each packaged die is marked and the reconstituted wafer is diced (singulated) into individual packages.
ANSYS Electronics Desktop (AEDT) is a multi-physics simulation software that combines Electromagnetic, Signal Integrity, Thermal and Electro-Mechanical simulation tools in a single integrated platform. It is widely used for designing and analyzing high-speed electronic circuits and systems.
We will be taking an already available FC-BGA package within the Icepak Toolkit for this simulation exercise.
- Step 1 : Open AEDT and launch Icepak
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- Step 2.1 : Create a Flipchip BGA Package
Icepak -> Toolkit -> Geometry -> Packages -> Flipchip_BGA
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- Step 2.2 : The Package Configuration window opens up
- The dimensions and other aspects of the package, substrate, die, die underfill and the solder balls can be configured here.
- Once configured, click OK to generate the package model.
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Package generated in Icepak  |
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- Step 3 : Explore the 3D Package Model Structure in Icepak
Ball Group  |
Substrate  |
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Die Underfill  |
Die  |
- Step 4 : Review and modify the material and definition types for the different components of the model.
Material Definitions  |
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- Step 5.1 : Add/ Assign Source Thermal Model for Die
- In "Project Manager" sub-window, expand Thermal section and open the BGA1_die_source and configure the thermal condition as shown below:
Source Thermal Model for Die  |
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- Step 5.2 : Add/ Assign Source Thermal Model for Substrate
- To add a thermal boundary condition for the substrate, right click on Flipchip_BGA1_substrate under
Models -> Flipchip_BGA1_Group -> Solidsand assign a Thermal Source. - Set the thermal condition on the substrate to Fixed Temperatue and the temperature as Ambient.
- To add a thermal boundary condition for the substrate, right click on Flipchip_BGA1_substrate under
Add Source Thermal Model for Substrate  |
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- Step 6 : Add Thermal monitors for the different components
- To add a Thermal monitor to the substrate, right click on the Flipchip_BGA1_substrate under
Models -> Flipchip_BGA1_Group -> Solidsand then chooseAssign Monitor -> Point... - In the sub-window that appears, select Temperature
- Repeat the same to add thermal monitors for the die and the die-underfill.
- To add a Thermal monitor to the substrate, right click on the Flipchip_BGA1_substrate under
Add Thermal monitor for Substrate  |
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Thermal monitors added  |
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Step 7.1 : Generate Mesh
- Go to the Simulation tab and click on
Generate Mesh - Save the project if prompted and wait for the mesh generation to get completed.
- Take a note of any error(s) and warning(s) that are shown and ignore/ take steps to debug & fix the issue(s) as required.
- Go to the Simulation tab and click on
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Step 7.2 : Review Mesh Quality metrics
- Once the mesh is generated, review the quality metrics of the generated mesh such as Face Alignment, Skewness and Volume.
Mesh Generation  |
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Mesh Quality - Face Alignment  |
Mesh Quality - Skewness  |
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Mesh Quality - Volume  |
- Step 8 : Add Thermal Analysis
- Under
Project Manager, right click onAnalysis and then, select Add Analysis Setupand configure the solver settings as required. (We will choose all default settings for our analysis)
- Under
Add Analysis Setup  |
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- Step 9 : Now, Validate the Simulation setup
- Click on the Validate button in the top ribbon
- Ensure all checks are validated successfully
Validate the setup  |
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- Step 10: Run the simulation and plot the temperature map
- Click on Analyze All button in the top ribbon
- Wait for the simulation to get completed successfully. Take note of any warning(s) or errors that may need further debug or setup modification(s).
- Once the simulation is completed, select the complete FC-BGA package in the 3D view by drawing a selection rectangle using the left-mouse button.
- Right click and then select
Plot Fields -> Temperature -> Temperature - Configure the different plot options:
- Specify Name, Folder
- Plot on Surface only
- Surface Smoothing -> Enable Gaussian Smoothing
Plot Fields  |
Field Plot Settings  |
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Field Plot - Top view  |
Field Plot - Bottom view  |
ICs are tested at multiple points during the manufacturing process to ensure they meet performance, reliability, and functionality requirements. Testing takes place both at the foundry and at OSAT facilities.
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1. Front-End Manufacturing
- Involves fabrication of integrated circuits on silicon wafers.
- Leads to fine tuning of the Process parameters to improve yield, reduce IDDQ/ leakage and improve speed/ performance.
2. Wafer Probe Test
- Wafer is mounted on a probe station and a probe card with makes contact with the bond pads or bump pads of each die.
- An ATE can now send test patterns to mark the die as good or bad.
1. Wafer Sorting
- Dies are sorted based on probe test results.
- Only functional dies proceed to packaging.
2. Package Manufacturing
- Functional dies are packaged
3. Package Testing
- Conducted in ISO Class 6/7 cleanroom zones
- Testing includes:
- AOST (Assembly Open and Short Test): Shorts/ Opens in Packages
- Burn-in Test: Elevated temperature and voltage and power cycling are applied to accelerate ageing to catch early failures.
- Final Test: Validate the electrical performance of the packaged IC across temperature and voltage corners and ensure it meets the datasheet specifications.
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4. System Level Testing (SLT)
- Testing is performed in conditions that closely mimic real-world system operation. SLT verifies how a chip behaves when it runs actual software or firmware inside a system-like environment.
1. Burn-In Test
- Burn-in testing is a reliability screening process where semiconductor devices are exposed to elevated temperatures, voltages, and operating conditions for an extended period to accelerate aging and failure mechanisms.
- It is used to identify and eliminate early-life failures (also called "infant mortality") in ICs before they are shipped to end users.
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2. Final Test (FT)
- Final Test is the last major electrical test phase after the semiconductor die has been packaged.
- It verifies that the packaged device meets all functional, parametric, and performance specifications before it is shipped to customers.
- It is typically performed by OSATs (Outsourced Semiconductor Assembly and Test providers) or in-house test facilities.
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Summary: ATE & Test Categories
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This is a hands-on lab to design a semiconductor wire bond package from scratch using Ansys Electronics Desktop (AEDT).
The main focus of this lab exercise is to build the complete cross-section of a wire bond package, including die, substrate, bonding wires, and mold compound, rather than performing any simulation or analyses.
Package Specifications:
| Component | Properties |
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| 1. Die |
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| 2. Substrate |
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| 3. Die Attach |
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| 4. Die Bond Pads |
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| 5. Substrate Bond Pads |
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| 6. Bond Wire |
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| 7. Mold Compound |
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- Step 1 : Launch AEDT and select Q3D (or Icepak, Maxwell 3D)
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- Step 2 : Define the working unit
Modeler -> Units...- Choose mm or um as the working unit for creating the model.
Set working Units  |
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Step 3.1 : Create the Die Geometry
- Select the rectangle tool from the ribbon or using the Menus (
Draw -> Rectangle) to draw a rectangle - Now, double click on CreateRectangle
Model -> Rectangle1to open up its Properties Dialog box. - Specify the position with one corner at the origin (0, 0, 0) and the dimensions as 3mm x 3mm
- Select
Model -> Rectangle1and from the menu bar:Modeler -> Surface -> Thicken Sheet...and set the thickness to 200 microns (0.2mm)
- Select the rectangle tool from the ribbon or using the Menus (
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Step 3.2 : Assign Material Properties
- Open up the Properties Dialog box either by double clicking on
Model -> Rectangle1 - Rename the geometry to Die
- Choose Silicon as the material from the Material Library.
- Open up the Properties Dialog box either by double clicking on
Die Geometry  |
Die Thickness  |
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Die Material  |
- Step 4.1 : Create the Substrate Geometry
- Draw another rectangle for the substrate (5mm x 5mm) and position (-1, -1, 0) it such that the die is at the center.
- Set the thickness as -500 microns (-0.5mm). Note the negative sign so as to have the substrate lie beneath the die.
- Adjust the substrate position along Z-axis to account for the die attach thickness. Adjusted position: (-1, -1, -0.1)
Substrate Geometry  |
Substrate Material  |
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Substrate position considering Die attach thickness  |
- Step 5 : Create the Die Attach Material
- Draw a rectangle of the same size as that of the die (3mm x 3mm) and at the same co-ordinates (0, 0, 0).
- Set the thickness to -100 microns (-0.1mm) as the DAM lies beneath the die and the substrate
- Assign the material to Modified Eopxy
- NOTE: Assign different shades/ colours to adjacent components to easily discern in 3D view.
Die Attach Material  |
Geometry  |
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Material  |
- Step 6 : Create Bond pads on Die and Substrate
- Draw a small rectangle and configure its size to to that of the die pad (0.2mm x 0.2mm). We will place the first Die Pad at the co-ordinates (0.2, 0.2, 0.2) so that it sits on top of the die and is at one of the edges.
- Set the thickness to 5 microns (0.005mm)
Die Bond Pad  |
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- Similarly, draw a small rectangle and configure its size to to that of the substrate bond pad (0.2mm x 0.2mm).
- We will place this Substrate Bind Pad at the co-ordinates (0.2, -0.7, -0.1) so that it sits aligned to the Die bond pad created in the previous step, and also on top of the substrate.
- Set the substrate bond pad thickness to 10 microns (0.010mm)
Substrate Bond Pad  |
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- Step 7 : Create Bond Wires
- Use the Bondwire tool under:
Draw -> Bondwire - Connect the centre of the Die Bond pad to the centre of the Substrate Bond Pad. It might be easier to draw the wires from the Top view orientation.
- Select the Bondwire type as JEDEC 4-point
- Assign gold as the Bondwire material
- Use the Bondwire tool under:
Draw the Bondwire connecting the die & substrate pad centers  |
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Gold Bondwire  |
Now, repeat the steps 6 and 7 to create and connect all the die and substrate bond pads using bondwires.
- Step 8 : Build the mold compound around the die
- Create a rectangular enclosure around the die and wires (5mm x 5mm, 1.2mm thickness)
- Position at (-1, -1, -0.1) covering the top side of the substrate.
- Set the thickness to 1.2mm so that it covers the die and the bondwires, while also leaving margin for any laser marking processes
Mold  |
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