v0.5.0beta0

• Supports logical lookup operations in IR and RTL codegen
  • Not yet supported in HLS codegen and DAIS interpreter
• Supports UnaryFunctionLUT, Softmax, MultiHeadAttention and LinformerAttention layers from HGQ2
  • masking functionality untested
• Various bug fixes
  • msb mux operation piplining
  • mul to constant presented as variable

Full Changelog: v0.4.1...v0.5.0beta0

v0.4.1

• Allow tracing with partial frozen inputs
• Remove unexpected batch dim extension for batchnorm layer in automatic model tracing

v0.4.0

• Add VHDL codegen 🎉 and verification through ghdl and verilator.
• !breaking rearrange codegen module layout.

v0.3.3

• Fix conversion in corner case where all input vector is collapsed
• Fix reduce function (mainly used in HGQ2 tracer)
• Standalone Vitis HLS codegen syntax fix

v0.3.2

• Support variable-variable multiplication
• Bug fixes
• More supported operation in HGQ2/Keras model trace
• Preliminary documentation page

v0.3.1

• Fix syntax error breaking in python 3.10
• Fix batchnorm axis computation in tracing
• Update default model synthesis script for Vivado

v0.3.0post1

• Syntax fix for __getitem__ in conv utils causing issue for py311-

v0.3.0

• Functional trace for common operations
  • end-to-end, model to verilog module/hls source conversion from hgq2 models
    • Dense/EinsumDense/Conv/Pooling/ReLU, plus common operators like add or sub.
  • And many low-level operators in keras v3 (e.g., direct a+/b * 2**n, ops.sum)
  • Overload FixedVariableArray for many numpy operations for internal tracing api.
• Extend DAIS with msb_mux ternary operator for min() and max() operations
• Bug fixes in verilog codegen, test coverage in hgq2 repo

v0.2.1

• Use numba list for latency and bw to support large inputs
• Allow multi-layers of registers for Fmax
• Overflow in constadd in some corner case
• Fix py313 numba type inference issue
• Syntax fix in item unpacking (and py310 compatibility)
• rm old heuristic decomposition

Full Changelog: v0.2.0...v0.2.1

v0.2.0

Full repository refactoring and algorithm update:

• Core CSE algorithm bugfix and update, smaller model now
• allowing hard_dc (hard delay constraint option)
• Lots of change in internal representation
• Verilog codegen supported with verilator binding for validation

Full Changelog: v0.1.2...v0.2.0