Jesd204 doc2

docs/library/axi_adxcvr/index.rst

@@ -0,0 +1,346 @@
+.. _axi_adxcvr:
+
+AXI_ADXCVR
+================================================================================
+
+.. hdl-component-diagram::
+   :path: library/xilinx/axi_adxcvr
+
+The AXI_ADXCVR is a utility core used to control and configure the highspeed
+transceivers.
+There are separate AXI_ADXCVR cores for Intel and Xilinx designs, due to the
+small differences between the Xilinx's and Intel's transceivers architecture.
+For the Xilinx architecture, the transceivers are instantiated in
+:ref:`UTIL_ADXCVR <util_adxcvr>`.
+
+
+Features
+--------------------------------------------------------------------------------
+
+-  Supports :git-hdl:`Intel <library/intel/axi_adxcvr>`
+   and :git-hdl:`Xilinx <library/xilinx/axi_adxcvr>` devices.
+-  Software can access the core's registers through an AXI4 Lite Memory Mapped
+   interface.
+-  Link reset and monitor for Intel and Xilinx.
+-  Reconfiguration interface control with broadcast capability for Xilinx.
+-  Access to the Statistical eye scan interface of the PHY (Xilinx).
+-  Supports up to 16 transceiver lanes per link (Xilinx).
+
+
+Intel Devices
+--------------------------------------------------------------------------------
+
+For Intel devices, the adi_jesd204 IP is using the axi_adxcvr core, which can be
+accessed by the **link_management** interface. It provides a global reset signal
+for the JESD204B framework. Resets the XCVR reset controller IP, the link PLL
+reset controller, the PHY itself, and also the link layer of the stack. Besides
+the reset generation, monitors the PLLs and the PHY state.
+
+
+Parameters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-parameters::
+   :path: library/xilinx/axi_adxcvr
+
+   * - ID
+     - Instance identification number, if more than one instance is used.
+   * - NUM_OF_LANES
+     - The number of lanes (primitives) used in this link.
+   * - XCVR_TYPE
+     - Refers to the transceiver speed grade 0-9.
+   * - FPGA_TECHNOLOGY
+     - Encoded value describing the technology/generation of the FPGA device
+       (e.g. Cyclone V, Arria 10, Stratix 10).
+   * - FPGA_FAMILY
+     - Encoded value describing the family variant of the FPGA device
+       (e.g. SX, GX, GT).
+   * - SPEED_GRADE
+     - Encoded value describing the FPGA’s speed-grade.
+   * - DEV_PACKAGE
+     - Encoded value describing the device package. The package might affect
+       high-speed interfaces.
+   * - FPGA_VOLTAGE
+     - Contains the value(0-5000 mV) at wich the FPGA device supplied.
+   * - TX_OR_RX_N
+     - If set (0x1), configures the link in transmit mode, otherwise receive.
+
+
+Interfaces
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-interfaces::
+  :path: library/xilinx/axi_adxcvr
+
+  * - s_axi_aclk
+    - System clock. (in general 100 MHz)
+  * - s_axi_aresetn
+    - System reset.
+  * - s_axi
+    - Slave AXI4 Lite Memory Mapped interface
+  * - up_ch_*
+    - | Connect logical port ``pll_locked`` to the fPLL’s **pll_locked** pin;
+      | Connect logical port ``ready`` to PHY reset controller.
+
+
+Register Map
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-regmap::
+   :name: INTEL_XCVR
+   :no-type-info:
+
+
+Software Guidelines
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+When the board powers up, both ATX and fPLL's must have a stable reference clock
+in order to lock automatically. If this requirement can not be respected by the
+system (e.g. the reference clocks are generated by a device that requires
+software configuration, through an interface implemented in FPGA), the software
+needs to reconfigure both PLLs, and just after that resets the transceivers.
+
+
+Xilinx Devices
+--------------------------------------------------------------------------------
+
+In Xilinx Devices, the core configures itself to be interfaced with the GT
+variant supported by the UTIL_ADXCVR core. All the transceiver primitives are
+configured and programmed identically.
+
+
+.. _parameters-1:
+
+Parameters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-parameters::
+   :path: library/xilinx/axi_adxcvr
+
+   * - ID
+     - Instance identification number, if more than one instance is used
+   * - NUM_OF_LANES
+     - The number of lanes (primitives) used in this link
+   * - XCVR_TYPE
+     - Define the current GT type, GTXE2(2), GTHE3(5), GTHE4(7)
+   * - FPGA_TECHNOLOGY
+     - Encoded value describing the technology/generation of the FPGA device
+       (7series/ultrascale)
+   * - FPGA_FAMILY
+     - Encoded value describing the family variant of the FPGA device(e.g., 
+       zynq, kintex, virtex)
+   * - SPEED_GRADE
+     - Encoded value describing the FPGA's speed-grade
+   * - DEV_PACKAGE
+     - Encoded value describing the device package. The package might affect 
+       high-speed interfaces
+   * - FPGA_VOLTAGE
+     - Contains the value(0-5000 mV) at wich the FPGA device supplied
+   * - TX_OR_RX_N
+     - If set (0x1), configures the link in transmit mode, otherwise receive
+   * - QPLL_ENABLE
+     - If set (0x1), configures the link to use QPLL on QUAD basis. If multiple
+       links are sharing the same transceiver, only one of them may enable the
+       QPLL.
+   * - LPM_OR_DFE_N
+     - Chosing between LPM or DFE of modes for the RX Equalizer
+   * - RATE
+     - Defines the initial values for Transceiver Control Register (REG_CONTROL
+       0x0008)
+   * - TX_DIFFCTRL
+     - Driver Swing Control(TX Configurable Driver)
+   * - TX_POSTCURSOR
+     - Transmitter post-cursor TX pre-emphasis control
+   * - TX_PRECURSOR
+     - Transmitter pre-cursor TX pre-emphasis control
+   * - SYS_CLK_SEL
+     - Selects the PLL reference clock source to drive the RXOUTCLK 
+       :ref:`Table 1 <axi_adxcvr table_one_label>`
+   * - OUT_CLK_SEL
+     - select the transceiver reference clock as the source of TXOUTCLK 
+       :ref:`Table 2 <axi_adxcvr table_two_label>`
+
+
+Interfaces
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-interfaces::
+   :path: library/xilinx/axi_adxcvr
+
+
+.. _register-map-1:
+
+Register Map
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. hdl-regmap::
+   :name: XCVR
+   :no-type-info:
+
+
+.. _software-guidelines-1:
+
+Software Guidelines
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The system must have active DRP and reference clocks before any software access.
+The software is expected to write necessary control parameters to LPM_DFE_N,
+RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1. After
+which monitor the STATUS bit to be set. There are no other requirements for
+initialization.
+
+The DRP access is identical for common and channel interfaces. The SEL bits may
+be set to a specific transceiver lane or 0xff to broadcast. A write to the
+CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read
+to this register has no effect. In order to write to the transceiver, set WR to
+0x1 with the address. In order to read from the transceiver, set WR to 0x0 with
+the address. As soon as this register is written, the BUSY signal is set and is
+cleared only after the access is complete. The broadcast read is a logical OR of
+all the channels. After an access is started, do NOT interrupt the core for any
+reason (including setting RESETN to 0x0), allow the access to finish itself.
+Though the core itself is immune to a software abort, the transceiver may fail
+on further accesses and may require a system-wide reset.
+
+The eye-scan feature also allows a SEL option and a broadcast has the effect of
+a combined mask. That is, the error counter will be zero ONLY if all the
+transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and
+wait for the same bit to self-clear. If eye-scan needs to be stopped, set the
+ES_REQ bit to 0x0.
+
+
+.. _axi_adxcvr table_one_label:
+
+Table 1
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. list-table::
+   :header-rows: 1
+
+   * - SYSCLK_SEL
+     - 00
+     - 01
+     - 10
+     - 11
+   * - GTXE2
+     - CPLL
+     - RESERVED
+     - RESERVED
+     - QPLL
+   * - GTHE3
+     - CPLL
+     - RESERVED
+     - QPLL1
+     - QPLL0
+   * - GTHE4
+     - CPLL
+     - RESERVED
+     - QPLL1
+     - QPLL0
+   * - GTYE4
+     - CPLL
+     - RESERVED
+     - QPLL1
+     - QPLL0
+
+.. _axi_adxcvr table_two_label:
+
+
+Table 2
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. list-table::
+   :header-rows: 1
+
+   * - OUTCLK_SEL
+     - 001
+     - 010
+     - 011
+     - 100
+     - 101
+     - All other combinations
+   * - GTXE2
+     - OUTCLKPCS
+     - OUTCLKPMA
+     - REFCLK
+     - REFCLK/2
+     - RESERVED
+     - RESERVED
+   * - GTHE3
+     - OUTCLKPCS
+     - OUTCLKPMA
+     - REFCLK
+     - REFCLK/2
+     - PROGDIVCLK
+     - RESERVED
+   * - GTHE4
+     - OUTCLKPCS
+     - OUTCLKPMA
+     - REFCLK
+     - REFCLK/2
+     - PROGDIVCLK
+     - RESERVED
+   * - GTYE4
+     - OUTCLKPCS
+     - OUTCLKPMA
+     - REFCLK
+     - REFCLK/2
+     - PROGDIVCLK
+     - RESERVED 
+
+The REFCLK selected by OUTCLK_SEL depends on the SYSCLK_SEL, it may be CPLL,
+QPLL0 or QPLL1 refclk.
+
+
+Physical layer PRBS testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
+PRBS generators and checkers allowing the testing the multi-gigabit serial link
+at the physical layer without the need of the link layer bringup.
+
+
+TX link procedure
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+#. Configure ref clock and device clocks for under test lane rate. Bring XCVR
+   out from reset.
+#. In the REG_PRBS_CNTRL registers set PRBSSEL to a non-zero value. See the
+   transceiver guides for exact values, different transceiver families may have
+   different encoding for the same pattern.
+#. On the receiving side of the link set the checker for the same pattern and
+   reset the error counters.
+#. No error should be recorded on the receiver side.
+#. Set the PRBSFORCEERR bit in the REG_PRBS_CNTRL register to force the error
+   injection into the stream of bits.
+#. The error should be detected and recorded on the receiver side.
+
+
+RX link procedure
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+#. Configure ref clock and device clocks for under test lane rate. Bring XCVR
+   out from reset.
+#. On the transmit side of the link set a test pattern that is available in the
+   receiving transceiver. Consult the transceiver documentation for details.
+#. In the REG_PRBS_CNTRL registers set PRBSSEL to the corresponding pattern.
+   Reset the error counters with PRBSCNTRESET.
+#. Check REG_PRBS_STATUS fields for results. If the check is successful for
+   non-GTX transceivers the PRBSLOCKED bit must appear as set and PRBSERR must
+   stay low. For GTX transceivers the PRBSLOCKED bit can be ignored and checking
+   the PRBSERR alone is sufficient. If PRBSERR is set, check with DRP accesses
+   the internal error counter to get the number of errors received. See the
+   transceiver guide for details.
+
+
+More Information
+--------------------------------------------------------------------------------
+
+-  :ref:`jesd204`
+-  :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
+
+
+Reference
+--------------------------------------------------------------------------------
+
+-  :intel:`Intel® Arria® 10 Transceiver PHY User Guide <content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf>`
+-  `7 Series FPGAs GTX/GTH Transceivers User Guide - Xilinx <https://docs.xilinx.com/v/u/en-US/ug476_7Series_Transceivers>`_
+-  `Ultrascale Architecture GTH Transceivers User Guide - Xilinx <https://docs.xilinx.com/v/u/en-US/ug576-ultrascale-gth-transceivers>`_

docs/library/index.rst

@@ -16,3 +16,6 @@ Contents
 
    axi_dmac/index
    spi_engine/index
+   jesd204/index
+   axi_adxcvr/index
+   xilinx/index