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Need Python 3 version of this library. No longer builds due to lack of use_2to3

#24

· Anutrix opened

on Jan 16, 2023

Error in parsing the last Output

#23

· Eyantra698Sumanto opened

on Jun 25, 2022

Does not look to be actively maintained

#21

· michael-etzkorn opened

on Sep 12, 2021

Documentation bug <code>extract_objects_from_source</code>

#20

· michael-etzkorn opened

on Sep 12, 2021

Parsing "output logic" port is wrong

#16

· masics opened

on Apr 17, 2020

matching end of entity and end of architecture

#13

· m-tosch opened

on Mar 17, 2019

Verilog and VHDL parser issues

#12

· nvzach opened

on Oct 2, 2018

verilog parser - parse as a port of a function's port.

#11

· KyleJeong opened

on May 26, 2018

verilog parser - Wrong parsing of comment

#10

· KyleJeong opened

on May 26, 2018

verilog parser - parsing when port name has "input_" characters

#9

· KyleJeong opened

on May 26, 2018

verilog parser struggled with 'output' as part of port name

#8

· Blechzwerg opened

on May 14, 2018

Get hdlparse registered at awesome-vhdl

#7

· Paebbels opened

on May 5, 2018