[hw,darjeeling] Add support for building a Verilator sim

hw/BUILD

@@ -5,6 +5,7 @@
 load("@rules_pkg//pkg:mappings.bzl", "pkg_files")
 load("//rules:fusesoc.bzl", "fusesoc_build")
 load("@rules_python//python:defs.bzl", "py_library")
+load("//hw/top:defs.bzl", "opentitan_select_top_attr")
 
 # This configuration exposes fusesoc's "verilator_options" option to the
 # command line. This is intended to allow CI to specifically build a single
@@ -100,9 +101,7 @@ fusesoc_build(
     ],
     data = ["//hw/ip/otbn:rtl_files"],
     make_options = ":make_options",
-    output_groups = {
-        "binary": ["lowrisc_dv_top_earlgrey_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
-    },
+    output_groups = opentitan_select_top_attr("top_verilator_binary"),
     systems = ["lowrisc:dv:chip_verilator_sim"],
     tags = [
         "manual",
@@ -177,7 +176,7 @@ filegroup(
         # dv_macros are needed by Ibex, so include this back in.
         "//hw/dv/sv:dv_macros",
         "//hw/ip:rtl_files",
-        "//hw/top_earlgrey:rtl_files",
+        "//hw/top:rtl_files",
     ],
     visibility = ["//visibility:public"],
 )

hw/top/BUILD

@@ -89,6 +89,11 @@ opentitan_alias_top_attr(
     attr_name = "otp_map",
 )
 
+opentitan_alias_top_attr(
+    name = "rtl_files",
+    attr_name = "top_rtl",
+)
+
 # For each top, create a selecting alias for the seed.
 [
     alias(

hw/top_darjeeling/BUILD

@@ -11,6 +11,16 @@ load(
 
 package(default_visibility = ["//visibility:public"])
 
+filegroup(
+    name = "rtl_files",
+    srcs = glob(["**"]) + [
+        "//hw/top_darjeeling/data:all_files",
+        "//hw/top_darjeeling/dv/verilator:all_files",
+        "//hw/top_darjeeling/ip:rtl_files",
+        "//hw/top_darjeeling/sw:all_files",
+    ],
+)
+
 filegroup(
     name = "doc_files",
     srcs = glob(["**/*.md"]) + [

hw/top_darjeeling/chip_darjeeling_verilator.core

@@ -0,0 +1,47 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:systems:chip_darjeeling_verilator:0.1"
+description: "Darjeeling toplevel for simulation with Verilator"
+filesets:
+  files_sim_verilator:
+    depend:
+      - lowrisc:systems:top_darjeeling:0.1
+      - lowrisc:systems:top_darjeeling_pkg
+      - lowrisc:ibex:ibex_tracer
+      - lowrisc:prim:clock_div
+      - lowrisc:systems:top_darjeeling_ast
+      - lowrisc:darjeeling_systems:scan_role_pkg
+      # TODO(#27347): prim_legacy_pkg is deprecated
+      - lowrisc:prim:prim_legacy_pkg
+      - lowrisc:prim_generic:all
+    files:
+      - rtl/chip_darjeeling_verilator.sv: { file_type: systemVerilogSource }
+
+parameters:
+  AST_BYPASS_CLK:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  default: &default_target
+    filesets:
+      - files_sim_verilator
+    parameters:
+      - AST_BYPASS_CLK=true
+    toplevel: chip_darjeeling_verilator
+    tools:
+      verilator:
+        verilator_options:
+          # required to support OTP constants
+          - "--max-num-width 131072"
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"

hw/top_darjeeling/defs.bzl

@@ -11,6 +11,8 @@ DARJEELING = opentitan_top(
     name = "darjeeling",
     hjson = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson",
     top_lib = "//hw/top_darjeeling/sw/autogen:top_darjeeling",
+    top_rtl = "//hw/top_darjeeling:rtl_files",
+    top_verilator_binary = {"binary": ["lowrisc_dv_top_darjeeling_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"]},
     top_ld = "//hw/top_darjeeling/sw/autogen:top_darjeeling_memory",
     otp_map = "//hw/top_darjeeling/data/otp:otp_ctrl_mmap.hjson",
     std_otp_overlay = DARJEELING_STD_OTP_OVERLAYS,

hw/top_darjeeling/dv/verilator/BUILD

@@ -0,0 +1,10 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)

hw/top_darjeeling/dv/verilator/chip_sim.core

@@ -0,0 +1,132 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:top_darjeeling_chip_verilator_sim:0.1"
+description: "Darjeeling toplevel for simulation with Verilator"
+virtual:
+  - lowrisc:dv:chip_verilator_sim
+
+filesets:
+  files_sim_verilator:
+    depend:
+      - lowrisc:dv_dpi_c:uartdpi
+      - lowrisc:dv_dpi_sv:uartdpi
+      - lowrisc:dv_dpi_c:gpiodpi
+      - lowrisc:dv_dpi_sv:gpiodpi
+      - lowrisc:dv_dpi_c:jtagdpi
+      - lowrisc:dv_dpi_sv:jtagdpi
+      - lowrisc:dv_dpi_c:dmidpi
+      - lowrisc:dv_dpi_sv:dmidpi
+      - lowrisc:dv_dpi_c:spidpi
+      - lowrisc:dv_dpi_sv:spidpi
+      - lowrisc:dv_verilator:memutil_verilator
+      - lowrisc:dv_verilator:simutil_verilator
+      - lowrisc:dv:sim_sram
+      - lowrisc:dv:sw_test_status
+      - lowrisc:dv:dv_test_status
+      - lowrisc:systems:chip_darjeeling_verilator
+    files:
+      - chip_sim_tb.sv: { file_type: systemVerilogSource }
+      - chip_sim_tb.cc: { file_type: cppSource }
+
+parameters:
+  RVFI:
+    datatype: bool
+    paramtype: vlogdefine
+    description: Enable the RISC-V Verification Interface and instruction tracing
+  VERILATOR_MEM_BASE:
+    datatype: int
+    paramtype: vlogdefine
+    description: Main memory mem base.
+  VERILATOR_TEST_STATUS_ADDR:
+    datatype: int
+    paramtype: vlogdefine
+    description: Verilator specific address to write to, to report the test status. This value should be at a word offset in the unmapped address space.
+  rom0init:
+    datatype : file
+    description : Application to load into Base ROM (in Verilog hex format)
+    paramtype : cmdlinearg
+  rom1init:
+    datatype : file
+    description : Application to load into Second ROM (in Verilog hex format)
+    paramtype : cmdlinearg
+  otpinit:
+    datatype : file
+    description : Image to load into the OTP (in Verilog hex format)
+    paramtype : cmdlinearg
+  ctnraminit:
+    datatype : file
+    description : Application to load into CTN RAM (in Verilog hex format)
+    paramtype : cmdlinearg
+  DMIDirectTAP:
+    datatype: bool
+    paramtype: vlogdefine
+    default: true
+    description: Replace JTAG TAP with an OpenOCD direct connection
+  UART_LOG_uart0:
+    datatype: str
+    paramtype: plusarg
+    description: Write a log of output from uart0 to the given log file. Use "-" for stdout.
+  RV_CORE_IBEX_SIM_SRAM:
+    datatype: bool
+    paramtype: vlogdefine
+    description: Disconnect the TL data output of rv_core_ibex so that we can attach the simulation SRAM.
+
+targets:
+  default: &default_target
+    filesets:
+      - files_sim_verilator
+    toplevel: chip_sim_tb
+
+  sim:
+    parameters:
+      - RVFI=true
+      - VERILATOR_MEM_BASE=0x10000000
+      - VERILATOR_TEST_STATUS_ADDR=0x211f0080
+      - rom0init
+      - rom1init
+      - otpinit
+      - ctnraminit
+      - DMIDirectTAP
+      - RV_CORE_IBEX_SIM_SRAM=true
+    default_tool: verilator
+    filesets:
+      - files_sim_verilator
+    toplevel: chip_sim_tb
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          # Disabling tracing reduces compile times but doesn't have a
+          # huge influence on runtime performance.
+          - '--trace'
+          - '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
+          # Remove FST options for VCD trace
+          - '--trace-structs'
+          - '--trace-params'
+          - '--trace-max-array 1024'
+          - '--unroll-count 512'
+          # TODO: Variable expansion depends on edalize internals. Find better solution.
+          #       (Applies to LDFLAGS expansion below as well)
+          - '-CFLAGS "$(CFLAGS_FOR_BUILD) -std=c++17 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb"'
+          - '-LDFLAGS "$(LDFLAGS_FOR_BUILD) -pthread -lutil -lelf"'
+          - '-Wall'
+          # Execute simulation with four threads by default, which works best
+          # with four physical CPU cores.
+          # Users can override this setting by appending e.g.
+          # --verilator_options '--threads 2'
+          # to the end of the fusesoc invocation when compiling the simulation.
+          - '--threads 4'
+          # XXX: Cleanup all warnings and remove this option
+          # (or make it more fine-grained at least)
+          - '-Wno-fatal'
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"

hw/top_darjeeling/dv/verilator/chip_sim_tb.cc

@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <algorithm>
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "verilated_toplevel.h"
+#include "verilator_memutil.h"
+#include "verilator_sim_ctrl.h"
+
+int main(int argc, char **argv) {
+  chip_sim_tb top;
+  VerilatorMemUtil memutil;
+  VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
+  simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
+                 VerilatorSimCtrlFlags::ResetPolarityNegative);
+
+  std::string dut_scope("TOP.chip_sim_tb.u_dut");
+  std::string top_scope(dut_scope + ".top_darjeeling");
+  std::string ram_name("gen_ram_inst[0].u_mem");
+  std::string ram1p_adv_scope("u_prim_ram_1p_adv." + ram_name);
+
+  MemArea rom0(top_scope + (".u_rom_ctrl0.gen_rom_scramble_enabled.u_rom.u_rom"
+                            ".u_prim_rom"),
+               0x8000 / 4, 4);
+  MemArea rom1(top_scope + (".u_rom_ctrl1.gen_rom_scramble_enabled.u_rom.u_rom"
+                            ".u_prim_rom"),
+               0x10000 / 4, 4);
+  MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4,
+              4);
+  MemArea ctn_ram(dut_scope + ".u_prim_ram_1p_adv_ctn." + ram_name,
+                  0x100000 / 4, 4);
+  MemArea otp(top_scope + ".u_otp_macro." + ram1p_adv_scope, 0x10000 / 4, 4);
+
+  memutil.RegisterMemoryArea("rom0", 0x8000, &rom0);
+  memutil.RegisterMemoryArea("rom1", 0x20000, &rom1);
+  memutil.RegisterMemoryArea("ram", 0x10000000u, &ram);
+  memutil.RegisterMemoryArea("ctn_ram", 0x41000000u, &ctn_ram);
+  memutil.RegisterMemoryArea("otp", 0x30000000u /* (bogus LMA) */, &otp);
+  simctrl.RegisterExtension(&memutil);
+
+  // The initial reset delay must be long enough such that pwr/rst/clkmgr will
+  // release clocks to the entire design.  This allows for synchronous resets
+  // to appropriately propagate.
+  // The reset duration must be appropriately sized to the divider for clk_aon
+  // in chip_darjeeling_verilator.sv.  It must be at least 2 cycles of clk_aon.
+  simctrl.SetInitialResetDelay(20000);
+  simctrl.SetResetDuration(10);
+
+  std::cout << "Simulation of OpenTitan Darjeeling" << std::endl
+            << "==================================" << std::endl
+            << std::endl;
+
+  return simctrl.Exec(argc, argv).first;
+}