LightRISCV

Single & Multi-cycle implementation of a subset of RISC-V for educational purposes.

The first version of this processor (multicycle) was adapted from the MIPS processor described in the Harris & Harris book¹. The single-cycle version was created from Bruno Levy's multicycle code², with signal names changed to match those in the book.

Instructions

make will simulate the single-cycle version. Be careful with data addresses, as the linker won't calculate them correctly. In the example below, s0 is manually set to the address of variable b instead of using the pseudo instruction la.

_start:
	addi s0, zero, 0x4 # Harvard architecture (monocycle)
	#la s0, b # Von Neumann architecture (multicycle)

Uncomment the following line if you want to simulate the multicycle version. In this version, the addresses are calculated correctly by the linker. To simulate this version, use the command make VERSION=MULTI.

Implemented instructions

• add
• addi
• lw
• sw
• jal (incomplete)

EDA Playground

• You can try it online here!

Further Reading

• Guia Prático RISC-V (pt-br)
• RISC-V Assembly Programming
• RARS: RISC-V Assembler and Runtime Simulator
• Digital Design and Computer Architecture: RISC-V Edition
• emulsiV: a visual simulator for a simple RISC-V processor
• DarkRISCV: Opensource RISC-V implemented from scratch in one night!

References

Footnotes

1. Digital Design and Computer Architecture ↩

2. From Blinker to RISC-V ↩