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@Purdue-SoCET Purdue System on Chip Extension Technologies

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    72 repositories

    • OS-dev

      Public
      C
      •0•0•0•0•Updated Oct 29, 2025Oct 29, 2025

    • atalla

      Public
      Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
      rtlcomputer-architectureco-designriscv64ppcisystolic-array
      SystemVerilog
      •
      Apache License 2.0
      •3•18•0•1•Updated Oct 29, 2025Oct 29, 2025

    • atalla-sim

      Public
      Cycle-Accurate Simulator of the Atalla-0x01
      emulatorsimulationperformance-modelingcycle-accurate-processor-simulation
      0•2•0•0•Updated Oct 29, 2025Oct 29, 2025

    • gpgpu-sim_distribution

      Public
      GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
      C++
      •
      Other
      •584•0•0•0•Updated Oct 29, 2025Oct 29, 2025

    • riscv-tests

      Public
      C
      •
      Other
      •518•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • riscv-test-env

      Public
      C
      •
      Other
      •119•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • RISCVBusiness

      Public
      SystemVerilog
      •
      Apache License 2.0
      •9•10•24•2•Updated Oct 28, 2025Oct 28, 2025

    • ttsky25b-intro-ii-calculator

      Public
      Purdue Intro II Binary Calculator (Spring 2025 project)
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • ttsky25b-intro-ii-audio-synthesizer

      Public
      Purdue Intro II Audio Synthesizer (Spring 2025 project)
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • gpu-design-logs

      Public
      This repository is the design log repo for GPU
      0•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • ttsky25b-intro-ii-stopwatch

      Public
      Purdue Intro II Stopwatch (Spring 2025 project)
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • ttsky25b-intro-ii-matrix-mult

      Public
      Purdue Intro II Matrix Multiplier (Spring 2025 project)
      SystemVerilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Oct 28, 2025Oct 28, 2025

    • embench-iot-aftx07

      Public
      The main Embench repository
      C
      •
      GNU General Public License v3.0
      •126•0•0•0•Updated Oct 27, 2025Oct 27, 2025

    • aihw-design-logs

      Public template
      Python
      •1•1•1•0•Updated Oct 27, 2025Oct 27, 2025

    • aihw-ppci-compiler

      Public
      A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
      Python
      •
      BSD 2-Clause "Simplified" License
      •41•1•5•2•Updated Oct 26, 2025Oct 26, 2025

    • SoCET-CI

      Public
      GitHub Action for Continuous Integration of SoC with FuseSoC
      Shell
      •0•0•0•1•Updated Oct 22, 2025Oct 22, 2025

    • FreeRTOS

      Public
      'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.
      C
      •
      MIT License
      •1.9k•0•0•0•Updated Oct 22, 2025Oct 22, 2025

    • RISC-V-CI

      Public
      Github actions for Continuous integration for RISC-V
      Shell
      •0•0•0•0•Updated Oct 20, 2025Oct 20, 2025

    • usb-host

      Public
      Repository for the USB Host project
      Makefile
      •0•0•0•0•Updated Oct 13, 2025Oct 13, 2025

    • intro-socet

      Public
      SystemVerilog
      •2•3•0•0•Updated Oct 12, 2025Oct 12, 2025

    • amp-llvm

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
      LLVM
      •
      Other
      •15k•0•0•0•Updated Sep 5, 2025Sep 5, 2025

    • verilator_tb_lab

      Public
      A lab designed to teach users how to write Verilator C++ testbenches
      C++
      •0•0•0•0•Updated Sep 4, 2025Sep 4, 2025

    • aihw-compiler

      Public
      0•0•0•0•Updated Sep 4, 2025Sep 4, 2025

    • FPU

      Public
      Floating-point unit for RISC-V core
      SystemVerilog
      •1•3•0•0•Updated Aug 8, 2025Aug 8, 2025

    • AES_accelerator

      Public
      Scala
      •0•0•0•0•Updated Jul 30, 2025Jul 30, 2025

    • Intro-to-SoCET-STM-Project

      Public
      This is the PCB for PCB onboarding of SoCET using KiCAD 9.0.
      0•0•0•0•Updated Jul 3, 2025Jul 3, 2025

    • chiplet-components

      Public
      SystemVerilog
      •0•3•0•0•Updated May 10, 2025May 10, 2025

    • xv6-rv32

      Public
      Port of MIT's xv6 OS to 32 bit RISC V
      C
      •
      Other
      •19•0•0•0•Updated May 10, 2025May 10, 2025

    • VGA-Project

      Public
      SystemVerilog
      •0•0•0•0•Updated May 4, 2025May 4, 2025

    • AXI-UVM

      Public
      SystemVerilog
      •0•1•0•0•Updated May 4, 2025May 4, 2025