BYU Configurable Computing Lab

All

56 repositories

bfasst
Public
Tools for FPGA Assurance Flows
VHDL
•
Apache License 2.0
•7•14•13•3•Updated Oct 29, 2025Oct 29, 2025
vtr-verilog-to-routing
Public
Verilog to Routing -- Open Source CAD Flow for FPGA Research
C++
•
Other
•430•1•0•0•Updated Oct 24, 2025Oct 24, 2025
neurocore_fpt_2025
Public
Python
•
Apache License 2.0
•0•0•0•0•Updated Oct 22, 2025Oct 22, 2025
byuccl.github.io
Public
BYU CCL website
HTML
•63•5•0•0•Updated Oct 16, 2025Oct 16, 2025
rand_soc
Public
Python
•0•0•0•0•Updated Oct 16, 2025Oct 16, 2025
BYU_PYNQ_PR_Video_Pipeline_Hardware
Public
BYU Pynq PR Video Pipeline Hardware
VHDL
•4•13•0•0•Updated Oct 2, 2025Oct 2, 2025
ddr_rowhammer
Public
Python
•
BSD 2-Clause "Simplified" License
•0•0•0•0•Updated Aug 18, 2025Aug 18, 2025
f4pga-xc-fasm2bels
Public
Library to convert a FASM file into BELs importable into Vivado.
Verilog
•
Apache License 2.0
•15•0•0•0•Updated Jul 7, 2025Jul 7, 2025
prjxray
Public
Documenting the Xilinx 7-series bit-stream format.
Python
•
ISC License
•161•1•0•0•Updated Jul 2, 2025Jul 2, 2025
yinstruments
Public
Python code to interact with lab instruments (power analyzer/oscilliscope)
Python
•2•1•1•0•Updated Apr 14, 2025Apr 14, 2025
PYNQ-PRIO
Public
Tcl
•
BSD 3-Clause "New" or "Revised" License
•6•15•0•0•Updated Apr 11, 2025Apr 11, 2025
WaFoVe
Public
Verilog
•1•3•0•0•Updated Feb 20, 2025Feb 20, 2025
spydrnet
Public
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
fpga digital hardware transformations eda circuits cad circuit hardware-designs transformation
Python
•
BSD 3-Clause "New" or "Revised" License
•23•101•44•1•Updated Feb 12, 2025Feb 12, 2025
polarfire-soc-bare-metal-examples
Public
Bare metal example software projects for PolarFire SoC
C
•20•0•0•0•Updated Dec 4, 2024Dec 4, 2024
prjxray-db
Public
Project X-Ray Database: XC7 Series
Makefile
•
Creative Commons Zero v1.0 Universal
•36•0•0•0•Updated Sep 7, 2024Sep 7, 2024
litex
Public
Build your hardware, easily!
C
•
Other
•662•0•0•0•Updated Aug 28, 2024Aug 28, 2024
short_circuit_aging
Public
Java
•
MIT License
•0•0•0•0•Updated May 19, 2024May 19, 2024
digital_design_colab
Public
Digital Design Colab Examples
Jupyter Notebook
•2•5•31•0•Updated Apr 16, 2024Apr 16, 2024
rowhammer-tester
Public
Python
•
Apache License 2.0
•16•0•0•0•Updated Feb 12, 2024Feb 12, 2024
litedram
Public
Small footprint and configurable DRAM core
Python
•
Other
•129•0•0•0•Updated Jan 29, 2024Jan 29, 2024
fpga-programmer
Public
Python
•0•1•0•0•Updated Jan 19, 2024Jan 19, 2024
spydrnet-tmr
Public
TMR utilities for the SpyDrNet project
fpga digital transformations verilog hardware-designs transformation netlist computer-aided-design fpgas electronic-design-automation
Python
•
BSD 3-Clause "New" or "Revised" License
•3•10•14•0•Updated Nov 7, 2023Nov 7, 2023
iprec
Public
Xilinx CoreGen module recognition project. Lead author Corey Simpson.
Python
•
Apache License 2.0
•1•2•2•2•Updated Sep 8, 2023Sep 8, 2023
bfat
Public
Bitstream Fault Analysis Tool
Python
•
Apache License 2.0
•2•15•8•1•Updated Jul 17, 2023Jul 17, 2023
mpsoc-rad-selftest
Public
0•0•0•0•Updated Mar 17, 2023Mar 17, 2023
edalize
Public
An abstraction library for interfacing EDA tools
Python
•
BSD 2-Clause "Simplified" License
•218•1•0•0•Updated Feb 2, 2023Feb 2, 2023
digital_design_colab_archive
Public archive
Jupyter Notebook
•
Apache License 2.0
•2•1•0•1•Updated Jan 27, 2023Jan 27, 2023
physical_netlist
Public
0•1•0•0•Updated Jan 18, 2023Jan 18, 2023
vcd_diff
Public
0•0•0•0•Updated Oct 11, 2022Oct 11, 2022
f4pga-classroom
Public template
Python
•3•3•0•0•Updated Oct 10, 2022Oct 10, 2022