Contains the submodules, IP-XACT files, mock RTL files, SystemC driver, Makefile for Verilator, and patch file for Kvazaar submodule Enables end-to-end HEVC encoding with HW HEVC simulation in the loop.
Whole workflow has been verified to work with Ubuntu 24.04.1 LTS.
After cloning this main repository, initialize the submodules and recursively fetch and checkout any nested submodules:
git submodule update --init --recursive
For the compilation and installation of libzmq, follow the instructions that can be found in the README.md of libzmq's repository.
- Note: if you want to use libzmq with Questa or Modelsim, the default compilers (gcc/g++) need to point to the ones provided with the installation of the chosen simulator.
For Kvazaar, first apply the patch to extend Kvazaar's functionality, enabling it to interface with the hardware simulation via libzmq sockets.
git -C kvazaar apply ../systemc/support_for_kvazaar_hw_simulation.patch
Then, follow the compilation and installation instructions that can be found in the README.md of kvazaar's repository.
Follow the download/installation instructions from SystemC Official Website
- Note: The SystemC driver and when using Verilator, has been verified to work with SystemC 3.0.0, most likely the newest up-to-date version will also work.
Follow the download/installation instructions from Veripool - Verilator
- Note: Verilator 5.020 2024-01-01 rev has been verified to work, most likely the newest up-to-date version will also work.
Kactus2 is the recommended tool for viewing the IP-XACT components and hardware designs in the repository. Follow the instructions that can be found in the README.md of the Kactus2 repository for compilation and installation.
Catapult is needed for generating the RTL level code from the high-level synthesis codes in uvgKvazaarHW_rtl_gen repository. Follow the instructions that can be found in the README.md of the uvgKvazaarHW_rtl_gen repository for generating the RTLs.
- Note: Catapult version 2024.1 has been verified to work, most likely the newest up-to-date version will also work.
Catapult is needed for generating the RTL level code from the high-level synthesis codes in uvgKvazaarHW_rtl_gen repository. Follow the instructions that can be found in the README.md of the uvgKvazaarHW_rtl_gen repository for generating the RTLs.
- Note: RTLs from the uvgKvazaarHW_rtl_gen need to be generated to
rtl/*at the root of uvgKvazaarHW repository
As of now, these files cannot be provided pre-compiled, and requires the user to have a license for using Catapult HLS-tool.
- Note: Kactus2 will show a warning for missing verilog files due to this.
For configuring the library in Kactus2, open the "Configure Library" from the tool bar and then add the root of this repository as a library path.
For opening the top-level hardware design:
- locate the
tuni.fi:subsystem:Kvazaar:1.0component, - right-click the component and select "Open HW Design",
- finally, choose either the "Hierarchical" or "Sim" view.
After opening the top-level hardware design in Kactus2, the RTL for the top-level design and recursively for all hierarchical designs introduced in the top-level can be generated by selecting "Generation" from the tool bar and then selecting "Verilog Generator".
- Note: Select the "Sim" hardware design view, when generating RTL for simulation purposes.
- Note:
tuni.fi/subsystem/Kvazaar/1.0/rtlandtuni.fi/subsystem/Kvazaar/1.0/simalready include the up-to-date generated RTLs for both "Hierarchical" and "Sim" view.
Either Verilator or Questa/Modelsim can be used for simulating all the generated RTLs.
Verilator:
- Locate the Makefile in systemc folder.
- Run
maketo verilate all RTLs to SystemC using Verilator into the "Kvazaar_Intra_Encoder_HW" folder, and then to compile the generated SystemC codes using the Verilator generated Makefile. - Alternatively, first run
make verilatefor verilation and thenmake simulationto compile the generated SystemC codes.
Questa:
- In Kactus2, select "Generation" from the tool bar, and then selecet "Modelsim Generation" to generate a "Kvazaar.do" file that will add all necessary files to an existing simulation project.
- By default, the "Kvazaar.do" file should be saved to
tuni.fi/subsystem/Kvazaar/1.0/, in that same folder is a file "Kvazaar_simulation.do", that will create the simulation project, add all files according to the Kactus2 generated .do file, configure the use of libzmq for the simulation, and start the compilation of all codes.
For Kvazaar to match the features of the HW HEVC intra encoder as closely as possible, the ultrafast preset can be used in all-intra mode.
Individual parameters corresponding the HW HEVC intra encoder as close as possible are the following:
-p 1 -n 1 --pu-depth-intra 1-4 --full-intra-search --no-rdoq --no-transform-skip --rd 0 --no-sao --no-deblock --no-signhide
Parameters affecting the HW HEVC encoding are --qp <int> for quantization parameter, and --pu-depth-intra <int>-<int> for the intra search range.
N number of threads are supported, but a sinlge HW HEVC intra encoder can only serve 16 CTUs in parallel. If using N > 16 threads, threads will served after previous ones have been served.
The simulation flow is the following:
- First start Kvazaar with the appropriate parameters,
- then start the HW simulation using either Questa/Modelsim or Verilator generated SystemC simulation,
- then wait for the simulation and HEVC encoding to finish (which will take some time depending on the resolution of the test sequence),
- finally, view and verify that the encoded HEVC bitstream is valid with a program that can decode HEVC.
If you use uvgKvazaarHW in your research, please cite the following paper:
P. Sjövall, G. Gautier, A. Mercat, and J. Vanne, “uvgKvazaarHW: Open-Source Hardware HEVC Intra Encoder,” in Proc. ACM Int. Conf. Computing Frontiers, Cagliari, Italy, May 2025.