Upgrade the Yosys+Odin-II Front-end#2148

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sdamghan wants to merge 34 commits intomasterfrom

enhance_yosys_odin_koios++

Commits on Sep 4, 2022

[Yosys+Odin-II]: enhance the Yosys script for performing the HDL elaboration by utilizing Yosys built-in coarse-grained synthesis
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[Yosys+Odin-II]: passing clock nodes intact to the partial mapper as they are introduced by recent changes
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[Yosys+Odin-II]: avoid concatenating the top module name to the edge sensitivity and the initial value of
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[Yosys+Odin-II]: - avoid resolving signle bit FF nodes as they already satisfied the partial mapper requirement
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[Odin-II]: avoid generating extra buf nodes while the top output drivers have the same name as top output signals
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[Yosys+Odin-II]: upgrade the Yosys script to utilize Yosys simplemap pass for basic operations.
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[Yosys+Odin-II]: - avoid instantiating logical not while there is a single bit width node in the partial mapper
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[Yosys+Odin-II]: - warn about undriven pins in Yosys coarse-grained BLIF file by BLIFReader
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[Odin-II]: fix a bug in printing netlist statistics
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[Yosys+Odin-II]: - add $clog2 to calculate address width in memory benchmarks located in regression_tests/benchmaks/common
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[Yosys+Odin-II]: regenerate expectation results of common and keywords benchmarks
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[Yosys+Odin-II]: regenerate expectation results of operators benchmarks
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[Yosys+Odin-II]: regenerate expectation results of FIR benchmarks
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[Yosys+Odin-II]: - regenerate expectation results of micro benchmarks
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[Yosys+Odin-II]: regenerate expectation results of syntax benchmarks
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[Yosys+Odin-II]: - regenerate expectation results of full benchmarks
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[Yosys+Odin-II]: regenerate expectation results of large, koios, and vtr benchmarks
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[Infra]: regenerate vtr_reg_yosys_odin golden results
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[Yosys+Odin-II]: fix cpp format
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[Doc]: update the documentaion for the Yosys+Odin-II upgraded script
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[Infra]: regenerate vtr_reg_yosys_odin golden results
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[Yosys+Odin-II]: update simulation output vectors for bm_match1_str_arch, bm_match4_str_arch, and bm_expr_all_mod
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[Yosys+Odin-II]: adding the Yosys full memory command instead of just collecting memory instances
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[Yosys+Odin-II]: - perform memory mapping in Odin-II partial mapper for multiport memory (regardless of the number of ports)
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[Yosys+Odin-II]: regenerate golden results
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[Yosys+Odin-II]: fix format issues
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[Docs]: update docs with recent changes in Yossys+Odin-II scripts
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[Yosys+Odin-II]: - fix a bug in receiving sv extension without having Yosys plugins installed
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[Yosys+Odin-II]: remove memory_share from Yosys script
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[Yosys+Odin-II]: regenerate expectation results of the common regression test
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[Yosys+Odin-II]: fix format issue
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[Docs]: resolve confilicts with the master branch update
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Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into enhance_yosys_odin_koios++
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[Docs]: resolve confilcts
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