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Merged
merged 44 commits into from
Dec 25, 2023

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poname
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@poname poname commented Dec 9, 2023

This PR organizes the koios benchmarks in VTR and addresses a few open issues.

The koios tests are divided into 4 groups according to size and design features: medium, large, proxy, and system-verilog (marked with *_medium, *_large, *_proxy, and *_sv).
Two frontends are supported: Parmys and Odin (marked with *_odin where possible).
The complex DSP features are disabled in tests marked as*_no_hb.

The medium and large categories are based on the original publication and #2419.
The large, proxy, and sv groups are added to weekly suite.
The medium group is added to nightly suite.
The proxy tests are from: koios_proxy_benchmarks.
The deepfreeze style tests require system-verilog parser and are tested separately.

The golden results for weekly suites are generated.
The target architecture for *_no_hb tests changed from k6_frac_N10_frac_chain_depop50_mem32K_40nm to k6FracN10LB_mem20K_complexDSP_customSB_22nm and golden results updated.
The koios ReadME file updated.
The developer guide on how to run the koios benchmarks updated.

Description

Koios benchmarks are tested by the following tasks in VTR:

Suite Test Description Target Complex DSP Features Config file Frontend Parser
Nightly Medium designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test4/koios_medium Parmys
Nightly Medium designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test4/koios_medium_no_hb Parmys
Nightly Medium designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test4_odin/koios_medium Odin
Nightly Medium designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test4_odin/koios_medium_no_hb Odin
Weekly Large designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_large Parmys
Weekly Large designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_large_no_hb Parmys
Weekly Large designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_large_odin Odin
Weekly Large designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_large_no_hb_odin Odin
Weekly Proxy designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_proxy Parmys
Weekly Proxy designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_proxy_no_hb Parmys
Weekly deepfreeze designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_sv Parmys System-Verilog
Weekly deepfreeze designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_sv_no_hb Parmys System-Verilog

The following are only for regression testing and less important for benchmarking:

Suite Test Description Target Complex DSP Features Config file Frontend
Strong A test circuit to check the architecture file k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_strong/koios_test Parmys
Strong Same test circuit without hard blocks k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_strong/koios_test_no_hb Parmys
Strong A test circuit to check the architecture file k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_strong_odin/koios_test Odin
Strong Same test circuit without hard blocks k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_strong_odin/koios_test_no_hb Odin
Nightly The conv_layer.v design multiple vtr_reg_nightly_test4/koios_medium_multi_arch Parmys
Nightly The conv_layer.v design multiple vtr_reg_nightly_test4_odin/koios_medium_multi_arch Odin
Nightly Other designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test6/koios_other Parmys
Nightly Other designs k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_nightly_test6/koios_other_no_hb Parmys
Nightly The bwave_like.fixed.small.v design multiple vtr_reg_nightly_test6/koios_other_multi_arch Parmys
Weekly The dla_like.large.v design k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_dla_large Parmys
Weekly The bwave_like.float.large.v design k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml vtr_reg_weekly/koios_bwave_float_large Parmys

Related Issue

#2416
#2401
#1782

These 2 issues can be closed since Yosys+Odin is removed from VTR and Parmys has no issues with the Koios benchmarks:
#2104
#2131

And this PR: #2148

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@poname
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poname commented Dec 20, 2023

@vaughnbetz This PR organizes the Koios benchmarks according to circuit size and design features.
And makes it easier to refer to specific settings in the future.
5 open issues and one old PR can be closed.
Missing golden results added, documents updated, and settings adjusted.
Please refer to the PR description for more details.

Ready to merge.

@poname poname marked this pull request as ready for review December 20, 2023 17:29
@poname poname changed the title [WIP] organize koios benchmark organize koios benchmarks Dec 20, 2023
@poname poname changed the title organize koios benchmarks Organize koios benchmarks Dec 20, 2023
@vaughnbetz
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Does the QoR gathering procedure at https://docs.verilogtorouting.org/en/latest/README.developers/#example-koios-benchmarks-qor-measurement have to change? Or is it still the same regtests that need to be run and parsed?

Adding @aman26kbm and @amin1377 for their comments.

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poname commented Dec 20, 2023

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Do we not want to add tasks that enable and disable hard_mem? That would help verify Parmys' memory inference features.

I am not sure, but I think I had those before.

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I added a few comments. Overall, this is a great effort. I appreciate all the work you've put in, @poname. Thank you very much!

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poname commented Dec 22, 2023

I added a few comments. Overall, this is a great effort. I appreciate all the work you've put in, @poname. Thank you very much!

You're welcome!

@poname poname requested a review from vaughnbetz December 22, 2023 17:57
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Looks good; thanks. Will merge once CI passes. The pull request labeler failed with some permission issue (strange); I will ignore that.

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poname commented Dec 22, 2023

Looks good; thanks. Will merge once CI passes. The pull request labeler failed with some permission issue (strange); I will ignore that.

Thanks!
These issues can be closed:
#2416
#2401
#1782

#2104
#2131

And this PR: #2148

@vaughnbetz vaughnbetz merged commit 5de9ba4 into verilog-to-routing:master Dec 25, 2023
@poname poname deleted the weekly-test-koios branch December 25, 2023 17:29
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3 participants