Add tileable RR Graph #3134

amin1377 · 2025-06-11T18:14:24Z

Merging OpenFPGA branch into master branch. PR #2135 explains features of OpenFPGA.

…le info

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-06-19T22:35:52Z

Hi @AlexandreSinger,

I think the PR is ready for your first round of review. I'd appreciate it if you could take a look. Thanks!

amin1377 · 2025-06-19T22:37:00Z

Hi @soheilshahrouz,

This PR is ready for your review. Since you're familiar with the RR Graph code, it would be great if you could take a look at the tileable RR Graph implementation.

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger

Hi @amin1377 thanks for bringing this in! I recognize not all of this is your code. Overall the code is well structured however it needs some code style and data structure cleanup so it can fit in better with the rest of the VTR flow.

Some. of the data structure changes can be made into issues; however, the coding style things should probably be fixed now.

doc/src/arch/reference.rst

doc/src/vpr/VIB.rst

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.h

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

amin1377 · 2025-06-23T15:06:17Z

QoR comparison:
Titan: Link
Large VTR: Link

…rilog-to-routing into add_tileable_rr_graph

… code

amin1377 · 2025-06-24T13:29:02Z

Thanks @AlexandreSinger; reviewing this amount of code is no small task, and I really appreciate your time. I've addressed your comments. Regarding your suggestions about replacing the vector of vectors with VTR data structures: while I agree with them in principle, I didn’t apply all of them since this part of the code is not performance-critical.

I think the code is now ready for the next round of reviews. I’ve also added @AmirhosseinPoolad to help with it.

soheilshahrouz

Thanks for this PR.
Since it's a large one, I’ve reviewed some files for now and will go through the rest soon.

libs/libarchfpga/src/physical_types.h

libs/libarchfpga/src/arch_util.cpp

libs/librrgraph/src/base/get_parallel_segs.h

libs/librrgraph/src/base/get_parallel_segs.cpp

libs/librrgraph/src/base/rr_graph_storage.h

libs/librrgraph/src/base/rr_graph_storage.cpp

libs/libarchfpga/src/read_xml_arch_file.cpp

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-06-25T21:31:09Z

@soheilshahrouz: Thank you for taking the time to review this PR. I’ve addressed all your comments, and I think this PR is now ready for the next round of review.

AlexandreSinger

Hi Amin, thanks for fixing my prior comments. The reward for good work is more work my friend. I am just kidding; I gave this another pass focusing more on the documentation since I only glanced over it in my last review.

AlexandreSinger · 2025-06-27T01:54:37Z

doc/src/VIB.rst

+
+VIB Architecture
+============
+The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing MUXes, whose inputs are driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes.


"In past" -> "In the past"
"switch blocks have" -> "switch blocks had"
"whose inputs are driven" -> "whose inputs were driven"

AlexandreSinger · 2025-06-27T01:55:55Z

doc/src/VIB.rst

+============
+The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing MUXes, whose inputs are driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes.
+
+Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure.


I think it would be a good idea to spell out what the acronym "VIB" means in this context. "Versatile Interconnect Block (VIB)" or something just so its written down somewhere on this page.

AlexandreSinger · 2025-06-27T01:57:57Z

doc/src/VIB.rst

+
+FPGA Architecture File Modification (.xml)
+--------------------------
+For original tags of FPGA architecture file see :ref:`fpga_architecture_description`.


I suggest: "For the original tags available for the standard FPGA architecture file see"

I feel like it can get confusing with all the architecture file words being thrown around.

AlexandreSinger · 2025-06-27T01:59:01Z

doc/src/VIB.rst

+    For example, a length 4 wire has a bent pattern of ``- - U``.
+    A ``-`` indicates no bent at this position and a ``U`` indicates a conterclockwise bent at the position. (``D`` indicates a clockwise bent.)
+
+    .. note:: A bent wire should remain consistent in both the x and y axes.


What does consistent mean in this context? If you know it may be a good idea to expand on this if this is important.

AlexandreSinger · 2025-06-27T02:00:03Z

doc/src/VIB.rst

+.. arch:tag:: <multistage_muxs>content</multistage_muxs>
+
+    :req_param content:
+    	The detaild information for first and second MUXes.


"detaild" -> "detailed"

AlexandreSinger · 2025-06-27T02:26:59Z

doc/src/arch/reference.rst

+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+
+In OpenFPGA architecture:


"In a tileable architecture:"

AlexandreSinger · 2025-06-27T02:28:36Z

doc/src/arch/reference.rst

+
+In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
+
+A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.


"implement his point to point connection" -> "implement their point to point connection"

Anyone can be designers 😄

"a truth table with our new parameters id provided below". Something is off about this sentence.

AlexandreSinger · 2025-06-27T02:34:09Z

libs/libarchfpga/src/read_xml_arch_file_vib.h

@@ -0,0 +1,11 @@
+#include <vector>


This file needs a pragma once.

AlexandreSinger · 2025-06-27T02:41:13Z

libs/librrgraph/src/base/rr_graph_view.h

+        return node_storage_.edge_sink_node(edge);
+    }
+
+    /** @brief Get the source node for the iedge'th edge from specified RRNodeId.


Missing a return-carriage just before the "@brief"

AlexandreSinger · 2025-06-27T02:54:55Z

vpr/src/base/setup_vib_grid.cpp

+
+    if (priority < max_priority_type_loc.priority) {
+        //Lower priority, do not override
+#ifdef VERBOSE


I am wondering if using VTR_LOG_DEBUG would be more appropriate and easier to work with.

amin1377 added 19 commits June 11, 2025 09:55

[vpr][rr_graph] add tileable rr graph dir

b6371d2

[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation

77781b4

[vpr][route] update rr_graph generation with tileable rr graph

cf95e2c

[vpr][util] add is_inter_cluster_node for vib arch

431923c

[vpr][route] update router lookahead with tileable rr graph

d62fb79

[vpr][blif] use regex to find param val

02a56e9

[vpr][base] update with tileable rr graph

204a794

[vpr][route] remove unused param

7edf56d

[lib][arch] add vib processing

f5e8061

[lib][arch] add vib_inf

14064c7

[libs][rr_graph] update lib rr graph with tileable

49b04b0

[libs][rr graph][io] update read/write rr graph functions with tileab…

c6df91a

…le info

[libs][rr graph][io] update rr_grpah utils with tileable info

bf19150

[lib][rr_graph] add vtr tokenizer

3970db7

[lib][util] update capnp and util with open fpga

797b488

add openfpga doc

cf2dbc8

[vpr][base] add vib grid

0e03dc7

add VIB doc

f8fae78

[vpr][route] fix alloc_and_load_rr_switch_inf definition

5462ccd

github-actions bot added VPR VPR FPGA Placement & Routing Tool libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code libvtrutil labels Jun 11, 2025

amin1377 added 6 commits June 11, 2025 14:15

make format

7cdf5bf

[vtr_flow][test] add openfpga arch

5ad8303

[CI] add openfpga tests

c79ab8f

fix formatting

8eccbcc

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

0cc6f10

…rilog-to-routing into add_tileable_rr_graph

[doc][arch] add tileable doc

5a492c8

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

837278b

…rilog-to-routing into add_tileable_rr_graph

amin1377 requested a review from AlexandreSinger June 19, 2025 22:36

amin1377 requested a review from soheilshahrouz June 19, 2025 22:37

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

7c6a979

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger requested changes Jun 20, 2025

View reviewed changes

amin1377 added 10 commits June 23, 2025 12:43

[libs][arch] fix c-style code in read_xml_arch_file

ca95008

[lib][arch] fix process_vib_block_type_locs style

bb9a338

[lib][arch] pass set funcitons params by reference

af27706

Apply code review comment

4194e81

make format

561a0d5

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

07d4bac

…rilog-to-routing into add_tileable_rr_graph

fix a typo

4e38274

[libs][arch] fix clang-17 warning

f324567

[vpr][route][tileable] replace VTR_LOG to VTR_LOG_DEBUG & fix c-style…

1f929ea

… code

[libs][vtrutil] fix string_view error

bc7ffcd

amin1377 requested a review from AmirhosseinPoolad June 24, 2025 13:29

soheilshahrouz requested changes Jun 24, 2025

View reviewed changes

amin1377 added 5 commits June 25, 2025 12:23

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

9cf3775

…rilog-to-routing into add_tileable_rr_graph

[vpr][utils] move StringToken under vtr util

5f1939c

[vpr][base] remove unnecessary auto

bd62d9f

[vpr] apply code format rules to tileable RR Graph files

1d1318d

[libs][arch] move vib arch functions to a separate file

4c60c9d

make format

70836c5

amin1377 requested a review from vaughnbetz June 26, 2025 17:38

AlexandreSinger reviewed Jun 27, 2025

View reviewed changes


		In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.

		A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.

Add tileable RR Graph #3134

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Add tileable RR Graph #3134

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amin1377 commented Jun 23, 2025

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amin1377 commented Jun 25, 2025

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amin1377 commented Jun 11, 2025 •

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