Flat Routing Visualization

[SamuelHo10]

Several changes were made for flat routing visualization.

Firstly, I modified the draw intra-logic block code so that the margins between blocks are absolute and not based on relative size. The intra-logic blocks are also now drawn to be not long and skinny, and instead must have a reasonable width-to-height ratio. Furthermore, the intra-logic blocks of maximum depth were previously not drawn. That has also been fixed.

To get the pin locations of intracluster RRNodeId, I made helper functions to convert RRNodeId into cluster_blk_id and pb_graph_pin. I also separated the code which draws edges and pins, primarily for readability and also to avoid repetition. The loops with clusternets were replaced with atomnets when flat routing is enabled. Lastly, for testing and debugging purposes, the ability to click on intracluster pins to highlight the net was added.

[amin1377]

@SamuelHo10:

Thank you for your changes! Could you please share some screenshots showing how the intra-logic connections are drawn? Also, it would be helpful if you could include a screenshot for the case when the flat-router is not enabled, just to ensure the default flow remains intact.

I’m currently testing this PR locally, but having the screenshots here would be useful for future reference.

[SamuelHo10]

For Future Reference,

Flat Routing Enabled:

Flat Routing Disabled

[vaughnbetz]

Looks good; some changes requested though.
As we discussed in the meeting, you should:

• fix the arrow direction (done I think)
• test more architecture files.
• Stratix IV: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/titan/stratixiv_arch.timing.xml (need to use with a titan benchmark; neuron is the smallest normal one, but titan_other has some smaller ones still)
• Stratix 10: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/titan/stratix10_arch.timing.xml (need to use a Stratix 10 mapped Titan design or a Titanium design)
• Artix 7: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/xilinx/7series_BRAM_DSP_carry.xml
• Z1000: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/zeroasic/z1000/z1000.xml
• The arch we use with Koios (hopefully the developer guide points you at the right task)

[soheilshahrouz]

@SamuelHo10
Thansk for this PR.

We recently added a coding style guide to the documentation. Please read the guide and make sure that the code is consistent with the style rules.

[amin1377]

Thanks, Samuel!

[SamuelHo10]

Thanks for the code reviews @amin1377 and @vaughnbetz. I've tried my best to improve the code documentation and clarity based on your suggestions. I still have yet to test the other architectures, so I will try to get that done as soon as possible.

@AlexandreSinger At our last meeting, you suggested revising the naming of the internal blocks. Previously, the format was pb_type->name [pb->name]. I've updated the code to align more closely with the hierarchical_type_name() function in vpr_types.h, so it now prints as pb_type->name[placement_index][mode_name].
Would this naming scheme be more helpful for your use case?