| Item | Parameter |
|---|---|
| Chip | RiscyD2 (softcore) |
| Arch | RV32IM |
| Freq | 100M |
| Flash | 48KB |
| RAM | 8KB |
Digilent Arty-A7 (with XC7A35TICSG324-1L FPGA)
- GCC (riscv64-unknown-elf-gcc)
- Picolibc
- riscyd2.h
- Vivado
- Build the core and load it to the board
- Compile the program
- Load it to the board using talk2d2.py
- Listen to the incoming data from the board using listen2d2.py
Minor modifications in tm_port.h:
printfis not used in favor of uart based printing (macro defined inmain.c)TM_GET_USis not used in favor of cycles based time measurement (defined inriscyd2.h)
https://github.com/wpmed92/TinyMaix-RiscyD2
| config | mnist | Note |
|---|---|---|
| O0 CPU | 18 | |
| O1 CPU | 12 |