netdev CI testing #6666
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Like what i40e driver initially did in commit 3106c58 ("i40e: Use batched xsk Tx interfaces to increase performance"), use the batched xsk feature to transmit packets. Signed-off-by: Jason Xing <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Use the common interface to see if the desc is the end of packets. If so, set IXGBE_TXD_CMD_EOP bit instead of setting for all preceding descriptors. This is also how i40e driver did in commit a92b96c ("i40e: xsk: add TX multi-buffer support"). Signed-off-by: Jason Xing <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The PPE (packet process engine) hardware block is available in Qualcomm IPQ chipsets that support PPE architecture, such as IPQ9574. The PPE in the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which are used to connect with external PHY devices by PCS. It includes an L2 switch function for bridging packets among the 6 ethernet ports and the CPU port. The CPU port enables packet transfer between the ethernet ports and the ARM cores in the SoC, using the ethernet DMA. The PPE also includes packet processing offload capabilities for various networking functions such as route and bridge flows, VLANs, different tunnel protocols and VPN. The PPE switch is modeled according to the ethernet switch schema, with additional properties defined for the switch node for interrupts, clocks, resets, interconnects and Ethernet DMA. The switch port node is extended with additional properties for clocks and resets. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Add description and high-level diagram for PPE, driver overview and module enable/debug information. Signed-off-by: Lei Wei <[email protected]> Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The PPE (Packet Process Engine) hardware block is available on Qualcomm IPQ SoC that support PPE architecture, such as IPQ9574. The PPE in IPQ9574 includes six integrated ethernet MAC for 6 PPE ports, buffer management, queue management and scheduler functions. The MACs can connect with the external PHY or switch devices using the UNIPHY PCS block available in the SoC. The PPE also includes various packet processing offload capabilities such as L3 routing and L2 bridging, VLAN and tunnel processing offload. It also includes Ethernet DMA function for transferring packets between ARM cores and PPE ethernet ports. This patch adds the base source files and Makefiles for the PPE driver such as platform driver registration, clock initialization, and PPE reset routines. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The BM (Buffer Management) config controls the pause frame generated on the PPE port. There are maximum 15 BM ports and 4 groups supported, all BM ports are assigned to group 0 by default. The number of hardware buffers configured for the port influence the threshold of the flow control for that port. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
QM (queue management) configurations decide the length of PPE queues and the queue depth for these queues which are used to drop packets in events of congestion. There are two types of PPE queues - unicast queues (0-255) and multicast queues (256-299). These queue types are used to forward different types of traffic, and are configured with different lengths. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The PPE scheduler settings determine the priority of scheduling the packet across the different hardware queues per PPE port. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Configure unicast and multicast hardware queues for the PPE ports to enable packet forwarding between the ports. Each PPE port is assigned with a range of queues. The queue ID selection for the packet is decided by the queue base and queue offset that is configured based on the internal priority and the RSS hash value of the packet. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
PPE service code is a special code (0-255) that is defined by PPE for PPE's packet processing stages, as per the network functions required for the packet. For packet being sent out by ARM cores on Ethernet ports, The service code 1 is used as the default service code. This service code is used to bypass most of packet processing stages of the PPE before the packet transmitted out PPE port, since the software network stack has already processed the packet. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Configure the default action as drop when the packet size is more than the configured MTU of physical port. Also enable port specific counters in PPE. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The PPE RSS hash is generated during PPE receive, based on the packet content (3 tuples or 5 tuples) and as per the configured RSS seed. The hash is then used to select the queue to transmit the packet to the ARM CPU. This patch initializes the RSS hash settings that are used to generate the hash for the packet during PPE packet receive. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
…pping Configure the selected queues to map with an Ethernet DMA ring for the packet to receive on ARM cores. As default initialization, all queues assigned to CPU port 0 are mapped to the EDMA ring 0. This configuration is later updated during Ethernet DMA initialization. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Initialize the L2 bridge settings for the PPE ports to only enable L2 frame forwarding between CPU port and PPE Ethernet ports. The per-port L2 bridge settings are initialized as follows: For PPE CPU port, the PPE bridge TX is enabled and FDB learning is disabled. For PPE physical ports, the default L2 forwarding action is initialized to forward to CPU port only. L2/FDB learning and forwarding will not be enabled for PPE physical ports yet, since the port's VSI (Virtual Switch Instance) and VSI membership are not yet configured, which are required for FDB forwarding. The VSI and FDB forwarding will later be enabled when switchdev is enabled. Signed-off-by: Lei Wei <[email protected]> Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
The PPE hardware counters maintain counters for packets handled by the various functional blocks of PPE. They help in tracing the packets passed through PPE and debugging any packet drops. The counters displayed by this debugfs file are ones that are common for all Ethernet ports, and they do not include the counters that are specific for a MAC port. Hence they cannot be displayed using ethtool. The per-MAC counters will be supported using "ethtool -S" along with the netdevice driver. The PPE hardware various type counters are made available through the debugfs files under directory "/sys/kernel/debug/ppe/". Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Add maintainer entry for PPE (Packet Process Engine) driver supported for Qualcomm IPQ SoCs. Signed-off-by: Luo Jie <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Octeontx2/CN10k MAC block supports DMAC filters. DMAC filters can be installed on the interface through ethtool. When a user installs a DMAC filter, the interface's MAC address is implicitly added to the filter list. To ensure consistency, this MAC address must be kept in sync with the pfvf->mac_addr field, which is used to install MAC-based NPC rules. This patch updates the pfvf->mac_addr field with the programmed MAC address and also enables VF interfaces to install DMAC filters. Signed-off-by: Hariprasad Kelam <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: NipaLocal <nipa@local>
During driver initialization disable stale DMAC filters in CGX/RPM set by firmware. Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Hariprasad Kelam <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: NipaLocal <nipa@local>
CGX/RPM driver supports 48 bits of DMA addressing. Update the DMA mask accordingly. Signed-off-by: Hariprasad Kelam <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: NipaLocal <nipa@local>
MAC address, Link modes (supported and advertised) and eeprom data for the Netdev interface are read from the shared firmware data. This patch adds debugfs support for the same. Signed-off-by: Hariprasad Kelam <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: NipaLocal <nipa@local>
tc_actions.sh keeps hanging the forwarding tests. sdf@: tdc & tdc-dbg started intermittenly failing around Sep 25th Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: NipaLocal <nipa@local>
Signed-off-by: Jakub Kicinski <[email protected]> Signed-off-by: NipaLocal <nipa@local>
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Reusable PR for hooking netdev CI to BPF testing.